Electron beam mask writer EBM-9500 for logic 7nm node generation

To follow Moore’s law and the trend of devices to keep shrinking, the nanotechnology industry is challenged in finding a suitable technique for the mass production of integrated circuits with critical dimension in the sub-10 nm range. At the time this project started, EUV lithography, that employs light with a wavelength of 13.5 nm and thus requires the scanner to be kept under vacuum, was encountering difficulties in making its way into high volume manufacturing. Therefore different technologies were being explored as alternative to EUVL. The European project Single Nanometer Manufacturing for beyond CMOS devices (SNM) [1] aims at developing a manufacturing platform that routinely provides sub-10 nm resolution. To achieve that, fabrication processes based on Nano Imprint Lithography (NIL) are investigated. NIL is a low cost, high resolution and high throughput patterning technique, suitable for the mass production of devices. In NIL, a UV-transparent stamp is pressed on top of a substrate covered with polymer, called the NIL resist. The features on the stamp are imprinted in this polymer, that hardens under the exposure of UV light. The features on the polymer are then transferred into the underlying substrate using etching processes. To fabricate these stamps, we propose to use electron beam induced deposition (EBID)...

In this paper, we will discuss patterning challenges of EUV lithography to apply 1xnm node DRAM. EUV lithography is positioned on essential stage because development stage for DRAM is going down sub-20nm technology node. It is time to decide how to make sub-20nm node DRAM. It will be the simplest and cost effective way to make device with matured EUVL. But in spite of world-wide effort to develop EUV lithography, the maturity of EUV technology is still lower than conventional ArF immersion lithography. So, DRAM manufacturers are considering several candidates such as DSA, DPT and MPT simultaneously. In addition, DRAM manufacturers are considering new cell layout and new memory also. For this study, we investigate process window and shadow effect across exposure field of sub-20nm node DRAM cell. We also performed an overlay matching experiment between 0.25NA EUV scanner and 1.35NA ArF immersion scanner. In addition, we will compare EUV lithography with ArF immersion DPT or SPT in view of patterning performance. Finally, we will discuss some technical issues to applying EUV lithography such as flare, resist LER, EUV OPC and illumination condition using 0.25NA EUV scanner.

Implementation of extreme ultra violet lithography (EUVL) for printing features of dimensions around 32nm and below has faced multiple challenges that have been overcome mostly through tool and process engineering. Currently, the main concern for implementation of EUVL in high volume manufacturing is related to stochastic defects, such as line bridges or breaks, which may occur randomly and have an impact on device performance.1 Photon shot noise, in addition to the inherent process variability and material non-homogeneities can lead to defects on the final patterned structures. As the pitch and critical dimension (CD) approach 32nm pitch and below, the dependency of stochastics defects increases exponentially. This paper fits within imec’s EUV stochastics and defectivity program, which investigates the key parameters for the generation and mitigation of defects from both a theoretical and practical approach. Initially, a reference process has been established and a methodology has been developed to capture and characterize bridge-type defects after pattern transfer into relevant layers for metrology and applications. Optical inspection and scanning electron microscopy (SEM) review are used to collect information on the number and types of defects present over large patterned areas (in the order of cm2). With a well-defined inspection technique, experiments related to fundamentals as well as materials and processes are continuously run. In the past years, imec has been leading the fundamental work on stochastic defects.2,3 De Bisschop et al. identified the “defect cliff”, or the exponential dependency of defect density as a function of space CD for multiple parameters, such as resist formulation and exposure/imaging conditions. More recently, the focus has changed to the investigation of the “defect floor”, which as the name suggests, is a flat response of defects to CD. The defect floor suggests that defectivity cannot be further improved, making one of the most relevant problems to solve for implementation of EUV in high volume manufacturing (HVM). Our results show a decomposition of the potential contributors to explore the effect of processing conditions related to scanner, track and pattern transfer on final defect density for a chemically amplified resist and attempt a comparison to a metal-oxide resist. Goal is to understand the contributors to the defect floor and identify an effective route to avoid/minimize defect formation.

Photomask used for optical lithography has been developed for purpose of fabrication a pattern along with finer designed rules and increase the productivity. With regard to pattern fabrication on mask, EB (Electron beam) mask writer has been used because it has high resolution beam. But in producing photomask, minimum pattern size on mask is hits a peak around 40nm by the resolution limit of ArF immersion systems. This value is easy to achieve by current EB writer. So, photomask process with EB writer has gotten attached to increase turnaround time. In next generation lithography such as EUV (Extreme ultraviolet) lithography and Nano-imprint lithography, it is enable to fabricate finer pattern beyond the resolution limit of ArF immersion systems. Thereby the pattern on a mask becomes finer rapidly. According to ITRS 2012, fabrication of finer patterns less than 20nm will be required on EUV mask and on NIL template. Especially in NIL template, less than 15nm pattern will be required half a decade later. But today’s development of EB writer is aiming to increase photomask’s productivity, so we will face a difficulty to fabricate finer pattern in near future. In this paper, we examined a potential of mask production process with EB writer from the view of finer pattern fabrication performances. We succeeded to fabricate hp (half-pitch) 17nm pattern on mask plate by using VSB (Variable Shaped Beam) type EB mask writer with CAR (Chemically Amplified Resist). This result suggests that the photomask fabrication process has the potential for sub-20nm generation mask production.

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

In 2019, finally, extreme ultraviolet (EUV) lithography has been applied to high volume manufacturing (HVM) for preparing advanced semiconductor devices. That was very important year for EUV enthusiasts and semiconductor industry. Because it takes for a long time, more than 30 years, to study EUV lithography for realizing HVM. With recent rapid progress on the source power improvement, EUV lithography development including photoresist materials has been achieved HVM requirements. However, the performance of EUV resist materials are still not enough for the expected HVM requirements, even by using the latest qualifying EUV resist materials. One of the critical issues is the stochastic issues, which will be become ‘defectivity’, like a nano-bridge or a nano-pinching. The analyzing summary of the stochastic factors in EUV lithography, and their improvement status are described in this paper. 2 (two) major stochastic issues, which are photon stochastic and chemical stochastic, were observed in the lithography steps. And the improvement status of each stochastic issues including lithographic results are also described.

Extreme ultraviolet (EUV) lithography is considered as the leading patterning technology beyond the ArF-based optical lithography, addressing the need for transistor densification to meet Moore's Law. Theoretically, EUV lithography at 13.5nm wavelength meets the resolution requirements for 1xnm technology nodes. However, there are several major challenges in the development of EUV lithography for mass production of advanced CMOS devices. These include the development of high power EUV light sources, EUV optics, EUV masks, EUV resists, overlay accuracy, and metrology and inspection capabilities. In particular, it is necessary to ensure that effective defect control schemes will be made available to reduce the EUV lithography defectivity to acceptable levels. This paper presents a study on the wafer defectivity and characterization of patterned EUV resists, with the objective of providing a quantitative comparison between the defectivity of different resist materials and different stacks. Patterned wafers were printed using the ASML® EUV full-field Alpha-Demo Tool (ADT 0.25 NA) at imec. The EUV resist patterns were 32nm line/spaces. Several advanced resist types were screened experimentally. The different resist types and stacks were inspected using a DUV laser based brightfield inspection tool, followed by a SEM defect review and CD metrology measurements. The patterns were characterized in terms of defect types and defect density. We identified the major defect types and discuss factors that affect the defectivity level and pattern quality, such as resist type, exposure dose and focus. Defect scattering analysis of DUV polarized light at different polarizations was performed, to indicate on the inspection performance trends for a variety of defect types and sizes of the different resists and stacks. The scattering analysis shows that higher defect scattering is induced using polarized light.

Pattern transfer by deep anisotropic etch is a well-established technique for fabrication of nanoscale devices and structures. For this technique to be effective, the resist material plays a key role and must have a high resolution, reasonable sensitivity, and high etch selectivity against the conventional silicon substrate or underlayer film. In this work, the lithographic performance of two high etch resistance materials was evaluated: ZEP520A (Nippon Zeon Co.) and mr-PosEBR (micro resist technology GmbH). Both materials are positive tone, polymer-based, and nonchemically amplified resists. Two exposure techniques were used: electron beam lithography (EBL) and extreme ultraviolet (EUV) lithography. These resists were originally designed for EBL patterning, where high quality patterning at sub-100 nm resolution was previously demonstrated. In the scope of this work, the authors also aim to validate their extendibility to EUV for high resolution and large area patterning. For this purpose, the same EBL process conditions were employed at EUV. The figures of merit, i.e., dose to clear, dose to size, and resolution, were obtained, and these results are discussed systematically. It was found that both materials are very fast at EUV (dose to clear lower than 12 mJ/cm2) and are capable of resolving dense lines/space arrays with a resolution of 25 nm half-pitch. The quality of patterns was also very good, and the sidewall roughness was below 6 nm. Interestingly, the general-purpose process used for EBL can be extended straightforwardly to EUV lithography with comparably high quality and yield. Our findings open new possibilities for lithographers who wish to devise novel fabrication schemes exploiting EUV for fabrication of nanostructures by deep etch pattern transfer.

Asahi Glass Company (AGC) has been developing the extreme ultra violet (EUV) lithography mask blank and polished substrate since 2003, including the developments of all essential materials and processes: the low thermal expansion material (LTEM), the material developments of the reflective, capping and absorber films, the process developments of the substrate polishing, cleaning, film deposition and resist film coating processes. In this paper, we present the current development status of the full-stack EUV mask blank and polished substrate which are the most suitable for the EUV lithography process development with EUV pre-production exposure tools. We report the development progress of the reflective multilayer-coated LTEM substrate by showing its critical performances with those of 2010 achievements, which include the substrate flatness, the EUV optical properties of the Mo/Si reflective layers and the defect of LTEM substrate and reflective layer. The performances of the Ta-based absorber and the resist films are explained as well to show the readiness of the EUV mask blank suitable for various kinds of process developments of the EUV lithography.

The rapid advancement of semiconductor manufacturing has driven the need for increasingly precise metrology and defect detection techniques. Extreme Ultraviolet (EUV) lithography, a key technology enabling the production of smaller and more efficient integrated circuits, introduces complex challenges in process control and defect inspection. Traditional methods struggle to keep pace with the heightened resolution and precision required for EUV-based semiconductor production. This paper explores the integration of machine learning (ML) techniques into EUV metrology and defect detection, offering a transformative approach to address these challenges. By leveraging advanced algorithms such as deep learning, neural networks, and data-driven models, we propose a new paradigm that enhances the detection of process-related defects, improves the accuracy of dimensional measurements, and provides real-time feedback for optimized manufacturing processes. The application of ML in this context not only enables more efficient defect classification and reduction but also offers the potential for predictive analytics that can proactively address emerging issues in EUV lithography. This shift towards machine learning-driven metrology represents a significant leap in semiconductor manufacturing, promising to enhance yield, reliability, and performance in next-generation integrated circuits.

Imprint lithography is an effective and well-known technique for replication of nano-scale features. Nanoimprint lithography (NIL) manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. DRAM memory is challenging, because the roadmap for DRAM calls for continued scaling, eventually reaching half pitches of 14nm and beyond. For DRAM, overlay on some critical layers is much tighter than NAND Flash, with an error budget of 15-20% of the minimum half pitch. For 14nm, this means 2.1-2.8nm. DRAM device design is also challenging, and layouts are not always conducive to pitch dividing methods such as SADP and SAQP. This makes a direct printing process, such as NIL and attractive solution. The purpose of this paper is to review the performance improvements related to overlay, resolution and pattern transfer. Improvements in overlay include control methods such as imprint force, mask to wafer tip/tilt and pneumatic controls at the wafer edge. We also introduce the pattern transfer scheme used to etch features with half pitches below 20nm.

Extreme ultraviolet (EUV) lithography with a 13.5 nm exposure wavelength is a leading candidate for the next-generation lithography because of its excellent resolution for 16 nm half pitch (hp) node devices and beyond. High sensitivity EUV mask pattern defect detection is one of the major issues to realize device fabrication with EUV lithography. First, to estimate targeted pattern defect detection size, a simulation for defect printability was carried out. In order to achieve the required inspection sensitivity applicable for 1X nm node, a projection electron microscopy (PEM) system was employed, which enabled us to do inspection in higher resolution and with higher speed in comparison to those of the conventional deep ultraviolet and electron beam inspection systems. By incorporating high electron energy and low optical aberration into the PEM, we designed a system for 16 nm hp node defect inspection. To guarantee the quality of the 16 nm node EUV mask, corresponding sized programmed defect masks were designed, and a PEM system defect detection was evaluated by using the current system for 2X nm generation.

The following topics are dealt with: low-power electronics; Internet of Things; integrated circuit design; video coding; integrated circuit manufacture; CMOS integrated circuits; field programmable gate arrays; magnetic sensors; calibration; power consumption.

Extreme ultraviolet (EUV) lithography is considered to be the most effective strategy for realize 7 nm generation manufacturing and beyond. A key factor for the realization of EUV lithography is the choice of EUV resist material that is capable of resolving below 15-nm half pitch with high sensitivity. Chemical Amplified Resist (CAR) using positive-tone development (PTD) is still one of the strongest candidates for EUV lithography. Recently, some researchers have reported concerns on the limitations in the performance of CAR materials. Consequently, there is a critical need for new chemistry and development of new resist materials. However, new resist materials still have lots of concerns for manufacturing, such like a non-CAR materials including metal resist. Therefore, CAR materials are still most important items for EUV lithography manufacturing. We’ve been developing negative-tone imaging (organic solvent development) with EUV exposure (EUV-NTI) for a long time. EUV-NTI has advantages for line-width roughness (LWR) due to their low swelling and dissolving smoothly. New EUV-NTI performances will be shown and also process condition progress will be updated. Also, the basic study will be reported, which is high absorption unit including materials for improving stochastic effect. We report herein recent progress of CAR materials, both positive-tone and negative-tone for EUV lithography.

Extreme ultraviolet (EUV) lithography is considered to be the most effective strategy for realize 7 nm generation manufacturing and beyond. With recent rapid progress on the source power improvement, process and material explorations are more and more accelerated to achieve HVM requirements. Therefore, a key factor for the realization of EUV lithography is the choice of EUV resist material that is capable of resolving below 15-nm half pitch with high sensitivity. It has been thought that the main challenge of EUVL is satisfying Resolution (R) – LWR (L) – Sensitivity (S) requirements simultaneously. On the other hand, recent reports indicate defectivity caused by stochastic effect have to consider as well as RLS-tradeoff improvement. For 7 nm node application, traditional chemically amplified resist (CAR) system is first candidate because of its well-studied property through KrF and ArF manufacturing process for many years, e.g. stability, metal contamination and post-litho process compatibility. However its low EUV absorption property enhancing photon-shot-noise (PSN) effect is one major disadvantage of conventional CAR system, especially for low dose resist process construction. In the past, several researches aiming high EUV absorption CAR system were reported, but material design and its lithographic performance still need detailed investigation. The present study aims to clarify how we can overcome RLS-tradeoff and reduce defects. Accordingly, we investigated the PSN effect using progress dependency study and material design requirements to achieve high EUV absorption resists. Lithographic results of high EUV absorption resists based on the study were also described.