Performance analysis of asynchronous dual mode logic using leakage power reduction techniques

While some leakage power reduction techniques require modification of the process technology, others are based on circuit-level optimizations and are applied at run-time. We focus our study on the latter and compare three techniques: input vector control, body bias control, and power supply gating. We determine their limits and benefits in terms of the potential leakage reduction, performance penalty, and area and power overhead. The leakage power savings trends considering technology scaling are also presented. Due to the differences in the properties of datapath logic and memory structures, different implementations are recommended. Finally, the use of the "minimum idle time" parameter, as a metric for evaluating different leakage control mechanisms, is shown.

This paper presents a system-level technique for embedded processor-based systems targeting both dynamic power and leakage power reduction using datapath width optimization. By means of tuning the design parameter, datapath width tailored to a given application requirement, the processors and memories are optimized, resulting in significant power reduction, not only for dynamic power but also for leakage power. In our experiments with several real embedded applications, power reduction without performance penalty is reported ranging from about 14.5% to 59.2% for dynamic power, and 21.5% to 66.2% for leakage power.

Design of half adder using integrated leakage power reduction techniques

One of the biggest problems in complicated and high-performance SoC design is management of energy and/or power consumption. In this chapter, we present energy management techniques in system design including HW and SW, SoC architecture and logic design. Dynamic power consumption is the major factor of energy consumption in the current CMOS digital circuits. The dynamic power consumption is affected by supply voltage, load capacitance and switching activity. We present approaches to controlling supply voltage, load capacitance and switching activity dynamically and statically in system architecture and algorithm design levels. We also discuss about the memory architecture for reducing power and energy in HW and SW co-design of SoC. In the future CMOS technology, leakage power consumption becomes dominant, because the threshold voltages are scaled as the transistor size shrinks. We summarize the techniques for reducing leakage power in system architecture design. The contents of the chapter include the following issues; (1) power and energy consumptions in SoC design, (2) tradeoff between energy and performance, (3) tradeoff among energy, QoS (i.e., latency and computational precision), reliability, and flexibility (4) techniques for reducing dynamic power consumption, and (5) leakage power reduction techniques

Welcome to the 11th ACM/IEEE International Symposium on Low Power Electronics and Design!.The 2006 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to the beautiful, on-the-lake setting of the Tegernsee area in Germany, within a one hour drive from Munich. On a par with this great location, a strong and diverse technical program features two keynote talks from leaders in the field, a technical panel, four embedded tutorials, and, new for this year, three half-day tutorials scheduled for the last day of the symposium.Dr. Christoph Kutter, Senior VP Products and Systems, Infineon Technologies, will give a keynote on design challenges for mobile communication devices. The Thursday keynote is given by Barry Dennington, Senior Vice President, NXP Semiconductors/CTO/SoC Design Technology, who will present an industrial view on the demands of a convergent communications, consumer and automotive market, the technology challenges a semiconductor company faces and the solutions that lead to actual products with a few examples. The Friday panel is titled "Flexibility and Low Power; a Contradiction in Terms?". Moderated by Peter Wintermayr, Editor in Chief of Markt and Technik, panelists Reiner Hartenstein, Univ. Kaiserslautern; Heinrich Meyr, RWTH Aachen Univ. and Chief Scientific Officer CoWare; and Steve Leibson, Tensilica, will discuss whether configurable or re-configurable computing offer solutions for low power design.The four embedded tutorials during the first two days of the conference are organized around two major themes: (1) low power circuit design and technologies; and (2) low power systems and energy management. Two embedded tutorials on sub-threshold design and variability/low power design from experts from MIT, University of Michigan, and IBM Research are paired with two others on energy harvesting for battery limited systems and low power portable applications from researchers from NEC Labs and University of California. New for this year, ISLPED will offer three half-day tutorials on hot topics such as leakage aware design, micropower analog design, and addressing fault-tolerance/variability and power issues from system to circuit levels. The tutorials feature presenters from OFFIS, Intel, University of North Carolina, Carnegie Mellon University, and IBM Research.Out of 214 submissions received in early March, only 75 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 26% for regular and short papers (56 papers), or 35% including 19 posters. Topics range from low power analog and RF design, power aware circuit design and tools, and architecture techniques for low power, to system and application level power management. The program is organized in twelve technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as two interactive poster sessions that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition of ISLPED, this year's event also includes exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. New for this year, the program includes an industry session that will highlight contributions showcased by companies participating in the ISLPED exhibits. Winning entries to the annual Low Power Design Contest will also be featured in a separate technical session.

Caches are known to consume a large part of total microprocessor power. Traditionally, voltage scaling has been used to reduce both dynamic and leakage power in caches. However, aggressive voltage reduction causes process-variation--induced failures in cache SRAM arrays, which compromise cache reliability. In this article, we propose FFT-Cache, a flexible fault-tolerant cache that uses a flexible defect map to configure its architecture to achieve significant reduction in energy consumption through aggressive voltage scaling while maintaining high error reliability. FFT-Cache uses a portion of faulty cache blocks as redundancy—using block-level or line-level replication within or between sets—to tolerate other faulty caches lines and blocks. Our configuration algorithm categorizes the cache lines based on degree of conflict between their blocks to reduce the granularity of redundancy replacement. FFT-Cache thereby sacrifices a minimal number of cache lines to avoid impacting performance while tolerating the maximum amount of defects. Our experimental results on a processor executing SPEC2K benchmarks demonstrate that the operational voltage of both L1/L2 caches can be reduced down to 375 mV, which achieves up to 80% reduction in the dynamic power and up to 48% reduction in the leakage power. This comes with only a small performance loss (<%5) and 13% area overhead.

Welcome to the 11th ACM/IEEE International Symposium on Low Power Electronics and Design!.The 2006 edition of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) welcomes you to the beautiful, on-the-lake setting of the Tegernsee area in Germany, within a one hour drive from Munich. On a par with this great location, a strong and diverse technical program features two keynote talks from leaders in the field, a technical panel, four embedded tutorials, and, new for this year, three half-day tutorials scheduled for the last day of the symposium.Dr. Christoph Kutter, Senior VP Products and Systems, Infineon Technologies, will give a keynote on design challenges for mobile communication devices. The Thursday keynote is given by Barry Dennington, Senior Vice President, NXP Semiconductors/CTO/SoC Design Technology, who will present an industrial view on the demands of a convergent communications, consumer and automotive market, the technology challenges a semiconductor company faces and the solutions that lead to actual products with a few examples. The Friday panel is titled Flexibility and Low Power; a Contradiction in Terms?. Moderated by Peter Wintermayr, Editor in Chief of Markt and Technik, panelists Reiner Hartenstein, Univ. Kaiserslautern; Heinrich Meyr, RWTH Aachen Univ. and Chief Scientific Officer CoWare; and Steve Leibson, Tensilica, will discuss whether configurable or re-configurable computing offer solutions for low power design.The four embedded tutorials during the first two days of the conference are organized around two major themes: (1) low power circuit design and technologies; and (2) low power systems and energy management. Two embedded tutorials on sub-threshold design and variability/low power design from experts from MIT, University of Michigan, and IBM Research are paired with two others on energy harvesting for battery limited systems and low power portable applications from researchers from NEC Labs and University of California. New for this year, ISLPED will offer three half-day tutorials on hot topics such as leakage aware design, micropower analog design, and addressing fault-tolerance/variability and power issues from system to circuit levels. The tutorials feature presenters from OFFIS, Intel, University of North Carolina, Carnegie Mellon University, and IBM Research.Out of 214 submissions received in early March, only 75 strong technical papers were accepted for presentation in paper or poster sessions, yielding an acceptance rate of 26% for regular and short papers (56 papers), or 35% including 19 posters. Topics range from low power analog and RF design, power aware circuit design and tools, and architecture techniques for low power, to system and application level power management. The program is organized in twelve technical sessions featuring long (30 min) and short (20 min) paper presentations, as well as two interactive poster sessions that will provide an additional venue for authors and symposium attendees to interact in an informal setting. Following the tradition of ISLPED, this year's event also includes exhibits featuring tools and methodologies from leading vendors of low power or power-aware design tools. New for this year, the program includes an industry session that will highlight contributions showcased by companies participating in the ISLPED exhibits. Winning entries to the annual Low Power Design Contest will also be featured in a separate technical session.

Modern embedded systems are often severely resource-constrained. In current research, the reduction of dynamic power has been the focus. However, with increased chip speed and density in submicron scale, the static (leakage) power consumption has become an increasingly significant fraction of the total. Indeed, a five-fold increase in leakage power per technology generation has been observed. At this pace, leakage power could soon equal dynamic power. In this paper, we investigate scheduling policies to reduce leakage power in real-time systems. We show that with simple scheduling techniques, overall leakage energy can be reduced by an order of magnitude.

Ultra low power portable electronic devices are the need of modern world. Portable devices need prolonged battery life, which can be achieved by reducing the power dissipation. Substrate bias effect is a leakage power reduction technique. It describes the changes in the threshold voltage with respect to change in source to bulk voltage. The substrate bias effect is used to control the leakage current. The reverse bias voltage widens the depletion region, due to which the threshold voltage increases. In this paper a single bit low power full adder has been proposed with substrate bias effect. Simulation of low voltage high performance hybrid single bit full adder cell also has been presented. By using the reverse biasing technique we have achieved power reduction in the single bit full adder cell. The power, delay and, power delay product (PDP) results have been obtained for proposed and existing designs with varying supply voltages. The proposed design shows PDP of 253.38fJ as compared to 277.23fJ of low voltage high performance hybrid single bit full adder cell at 1.8 Vdd. Simulation result show that the proposed design also performs better at varying temperature conditions. The power delay product has been also plotted versus the different reverse bias voltages applied in the proposed technique. All the work has been done in 180nm CMOS technology.

A large amount of leakage power could be saved by increasing the number of idle virtual channels (VCs) in a network-on-chip (NoC). Low-leakage power switch is proposed to allow saving in power dissipation of the NoC. The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive virtual channel technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating (PG) reduces the average leakage power consumption of proposed switch. The proposed techniques save up to 97% of the switch leakage power. In addition, the dynamic power is reduced by 40%. The traffic-based virtual channel activation (TVA) algorithm is used to determine the traffic status and send adaptation signals to PG units to activate/deactivate the VCs. The TVA algorithm optimally utilizes VCs by deactivating idle VCs to guarantee high-leakage power saving with high throughput. TVA is an efficient and flexible algorithm that defines a set of parameters to be used to achieve minimum degradation in NoC throughput with maximum reduction in leakage power. The whole network average leakage power has been reduced by up to 80% for 2-D-mesh NoC with throughput degradation within only 1%. For 2-D-torus NoC, a saving in power of up to 84% is achieved with <2% degradation in throughput. The implementation overhead of TVA is negligible.

In sub-70 nm technologies, leakage power becomes a significant component of the total power. Designers address this concern by extensive use of adaptive voltage scaling techniques to reduce dynamic as well as leakage power. Low-power scan test schemes that have evolved in the past primarily address dynamic power reduction, and are less effective in reducing the total power. We propose a power-managed scan (PMScan) scheme which exploits the presence of adaptive voltage scaling logic to reduce test power. We also discuss some practical implementation challenges that arise when the proposed scheme is employed on industrial designs. Experimental results on benchmark circuits and industrial designs show a significant reduction in dynamic and leakage power. The proposed method can also be used as a vehicle to trade-off test application time with test power by suitably adjusting the scan shift frequency and scan-mode power supplies.

Many image/video processing algorithms require FIFO for filtering. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. We have proposed an energy- and area-efficient FIFO design for image/video applications through FIFO with error-reduced data compression (FERDC) and near-threshold operation. On architecture level, FERDC technique is proposed to reduce the size and power consumption of the FIFO by utilizing the spatial correlation between neighboring pixels and performing error-reduced data compression together with quantization to minimize the mean square error (MSE). On circuit level, near-threshold operation is adopted to achieve further power reduction while maintaining the required performance. To demonstrate the proposed FIFO, it has been implemented using a 0.18-μm CMOS process technology. The implementation covers different FIFO length, including 128, 256, 512, and 1024. The experimental results show that the proposed FIFO operating at 0.5 V and 28.57 MHz achieves up to 99%, 65%, and 34.91% reduction in dynamic power, leakage power, and area, respectively, with a small MSE of 2.76, compared with the conventional FIFO design. The proposed FIFO can be applied to a wide range of image/video signal processing applications to achieve high area and energy efficiency.

SRAM is widely used cache memory in the world. Materialization of low power SRAM with highest stability is a need of the hour. As from many years the requirement of fast and low power devices are augmenting. In this paper, in first part described about stability analysis from ADM (extract from N-Curve). After that information about leakage power is given. One 8T SRAM circuit is proposed with low power and highest probable stability. This paper promises reduction in power by 66%. The stability of the cell is also increased, i.e. WNM increased by 15.9%; penalty is in RNM by 7.9 %.

This paper addresses bitwidth optimization focusing on leakage power reduction for system-level low-power design. By means of tuning the design parameter, bitwidth tailored to a given application requirements, the datapath width of processors and size of memories are optimized resulting in significant leakage power reduction besides dynamic power reduction. Experimental results for several real embedded applications, show power reduction without performance penalty range from about 21.5% to 66.2% of leakage power, and 14.5% to 59.2% of dynamic power. key words: Bitwidth optimization, leakage power reduction, dynamic power reduction

Leakage power reduction in nano-CMOS designs has gained tremendous interest both in academia and industry. Many techniques have been proposed in the literature for leakage power reduction and one of the prominent techniques for leakage power reduction is the use of sleep transistors as power-gating elements to cut-off sub-threshold leakage current in circuits when they are in stand-by mode. Although sleep transistor insertion is very effective in cutting-off leakage, it also incurs timing, area and routing overhead. Since most of the sleep transistor insertion methodologies do post layout insertion, care should be taken such that there is minimal perturbation of the original layout. Over design of sleep transistors cells and sub-optimal sleep transistor placement must be avoided to achieve final design closure. Since the sleep transistor area plays an important and prominent role in this aspect, it necessitates for optimal sleep transistor sizing and synthesis technique under area constraints. In this paper, we first provide a methodology for optimal sleep transistor synthesis under given area constraints. We then apply our technique to the general timing and area constraint driven row-based power-gating methodology proposed in [13] and show how optimal low leakage designs with constraints on timing and area can be designed.