Performance-Directed Retiming for FPGAs Using Post-Placement Delay Information

High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation

Content-addressable memory (CAM) is a high-speed lookup memory, which searches the entire memory in parallel and provides address of the input search word. Internet of things (IoT) technology needs access control list filters, deployed using CAM, to reduce the flow of invalid data through the network. Field-programmable gate arrays (FPGAs) play an important role to provide the computational power to IoT nodes using ultra low power modern devices. CAMs are emulated in FPGAs using different memories, i.e., block RAM, distributed RAM, and flip-flops (FFs). FPGA-based CAMs have large power consumption due to the involvement of each CAM cell in parallel comparison. This work presents a bank-selective strategy for gate-based binary CAM on FPGA, which reduces the amount of comparisons and reduces power consumption on target FPGA device. For every input search key, only one bank is activated using gated-clock to compare the input key to corresponding stored rules. A sample of 512 x 36 of the proposed architecture with four banks is implemented on Xilinx Virtex-6 FPGA that consumes 42% less dynamic power compared to the best available CAM designs. Hardware resources of the proposed CAM design on target FPGA is reduced in terms of slice registers (SRs) and lookup tables (LUTs) by 7.9% and 8.8%, respectively, compared with the latest prior work.

The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

This chapter presents the design and evaluation of template-based Coarse-Grained Reconfigurable Array (CGRA) generated accelerators that process Orthogonal Frequency-Division Multiplexing receiver blocks. The CGRA operates as a coprocessor with a Reduced Instruction-Set Computing (RISC) processor so that the overall system yields the benefits of general- and special-purpose processing. The accelerators are designed by crafting the CGRA template to the computational and communication requirements of the algorithms in an effort to minimize the resource utilization and power dissipation on the target Field Programmable Gate Array (FPGA) device. The performance of each CGRA is recorded in terms of the number of clock cycles and several multiple performance metrics. The power consumption is also estimated by simulating the postfit gate-level FPGA netlist of the accelerators.

In this paper, we implemented the Discrete Wavelet Transform (DWT) for signal noise reduction on a Field Programmable Gate Array (FPGA) device, and combined the DWT module with the audio codec on the Cyclone-II EP2C35F72C6 FPGA on the Altera DE2 board connected to the chip. The signal was denoised by applying the thresholding only to the detail part of the DWT result. The results reveal the efficiency of our system design

With the continuous scaling down of very large scale integrated (VLSI) technologies and increased die size, the transistors are much smaller, and hence much faster. On the other hand, interconnects are narrower. So they are more resistive and slower in transmitting signals. This trend has led the interconnect delay to become a significant factor in determining the performance of VLSI designs. As the die size becomes larger, global interconnect length becomes longer. Thus, global interconnect delay is beginning to dominate a larger portion of the overall system performance. In order to take the impact of interconnect delay into account, it is very important to have computationally inexpensive and accurate interconnect delay models. The primary contribution of this thesis is to present two new interconnect delay models, called the Fitted Elmore Delay (FED) and the Improved Effective Capacitance Metric (IECM). The FED model is a simple, efficient and reasonably accurate interconnect performance estimation model. This model uses a curve fitting technique to approximate the accurate Hspice delay data. The functional form used in the curve fitting is derived based on the Elmore Delay (ED) model. Thus, our model has all the advantages of the Elmore Delay model. It has a closed form expression as simple as the ED model and is extremely efficient to compute. More importantly, it is significantly more accurate than the ED model. In fact, because of its striking similarity to the ED model, optimization of the delay with respect to the design parameters can be easily done. When applied to interconnect optimization techniques (i.e., wire sizing), the FED model is three to four times more accurate than the Elmore Delay model. On the other hand, like the ED model, the FED has the limitation of ignoring the resistive shielding problem. This problem occurs when the gate no longer sees the total net capacitance due to the high interconnect resistance. The Improved Effective Capacitance Metric (IECM) overcomes the resistive shielding problem. We adopt the methodology of computing the first three Taylor series coefficients of the driving-point admittance in the circuit. The IECM uses these Taylor coefficients to derive a closed form solution for the effective capacitance that captures the resistive shielding characteristics. The IECM can be implemented with similar simplicity as the Elmore Delay model. We have tested the IECM on a single-load circuit and multiple tree topologies. Experiments show that our model is significantly more accurate than

The Pietra-Ricci index detector (PRIDe) has been recently proposed as one of the simplest techniques for centralized, data-fusion cooperative spectrum sensing, attaining robustness against time-varying signal and noise levels, constant false alarm rate, and high detection power. In this paper, we propose the design and implementation of the PRIDe detector, targeting field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) solutions. Novel approaches are proposed for computing the PRIDe’s test statistic, including the absolute value of complex quantities, the complex multiplier-accumulator, and the spectrum occupancy decision. The absolute value operation, which is critical to the PRIDe test statistic computational cost, applies the coordinate rotation digital computer (CORDIC) algorithm as a low latency and resource-efficient option. Register transfer level (RTL) and Monte Carlo simulations show that the resulting ultra-low latency PRIDe detector architectures attain no performance loss with respect to floating-point simulations. One of the two proposed ASIC design versions of the PRIDe sensor occupies 34.9% lower area compared to the most area-efficient sensor reported in literature, whereas the other one is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.7\times$</tex-math> </inline-formula> faster than the fastest state-of-the-art sensor. In a nutshell, the proposed detector architecture delivers the highest area and power efficiencies, considering the scaled values of area-time product (ATP) and power-delay product (PDP) metrics, in comparison to implementations reported to date.

Coupling Of Synthesis And Layout: Challenges And Solutions

In this paper we present a constraint-model for pipelined digital signal processors, based on mathematical programming. Our intention is to maximize the utilization of allocated hardware components by minimizing the clock-cycle time and the period of cyclic innermost loop schedules in one approach. The constraint formulations are developed for a very general multiphase clocking environment with an FPGA (Field Programmable Gate Array) target architecture. >

Interconnect delays represent an increasingly dominant portion of overall circuit delays. During timing-driven physical synthesis process, timing analysis is repeatedly performed over several hundred thousand components. Thus, fast and accurate estimation of interconnect delays is crucial. Traditionally, lumped and elmore delay models have been widely used for computing interconnect delays in physical synthesis due to their computational efficiency. However, these delay models are known to be inaccurate since they ignore slew and resistive shielding effects. In this paper, we propose a new iterative refinement based delay estimation approach that considers resistive shielding along with driver slew. Experimental results show that the proposed approach gives not only highly accurate results for far end RC-line delays but also compares very favorably to more difficult to match source end delays and source slews. In addition, use of the proposed delay model in physical synthesis yields significant performance improvement on several large industrial ASICs.

The purpose of this paper is to demonstrate that adequate delay modeling of Field Programmable Gate Array (FPGA) elements, together with time borrowing techniques, can be effectively used to define the lowest power supply voltage (V DD ) value that allows correct functionality to be assured, within a specified system performance. One of the key techniques to lower dynamic power consumption is V DD down scaling. However, this has a significant impact on system performance. Operational conditions induce Power Supply Noise and thermal variations, which also impact system performance. In a previous paper, element and path propagation delay variation models for Altera Cyclone III FPGAs have been presented, which allow accurate performance versus V DD characterization. In this paper, the extension of the models to Xilinx Spartan-3A FPGAs is first described. Then, the proposed models, time borrowing techniques and FPGA standard resources are used to extend the ability of these devices to operate at lower V DD . Experimental results are presented, obtained in a circuit that includes the c432 ISCAS-85 benchmark, implemented in Cyclone III and Spartan-3A FPGAs using standard FPGA resources and vendor design tools. Results show that the same performance can be guaranteed under lower core V DD values (more than 33% below its nominal value, in the case studies), leading to a significant power consumption saving.

A systolic architecture for calculating the discrete Fourier transform (DFT) is described which is based on a new matrix formulation that decomposes the transform into sets of 4-point transforms. The architecture supports transform lengths that are not powers of two or based on products of coprime numbers. Compared to previous systolic implementations, the architecture is computationally more efficient and uses less hardware. It provides low latency as well as high throughput, and can do both 1D and 2D DFTs. An automated CAD tool was used to find latency and throughput optimal designs that matched the target field programmable gate array structure and functionality.

The most widely used open-source field programmable gate array (FPGA) placement and routing tool is the Versatile Packing, Placement and Routing (VPR) software developed at the University of Toronto, Canada. VPR calculates area and timing using target FPGA architecture and physical information. However, it cannot be used in FPGA IP design efficiently for two reasons. First, VPR cannot directly support most newly developed FPGA architectures, and modifying the C-coded VPR so that it can be used to evaluate a number of new architectures is time consuming. Second, the accuracy of the VPR performance results is inadequate for the evaluation of a complete FPGA IP in a design that targets the production of LSI. We propose an FPGA design framework that is focused on improving FPGA IP design efficiency. A novel FPGA routing tool is developed in this framework, namely the EasyRouter which uses the C# language. When an object-oriented programming method is used, there is less source code and it is easier to manage compared to VPR, thus shortening the development time. By using simple HDL code templates, EasyRouter can automatically generate the entire HDL code for a chip and the configuration bitstream. With these files, the FPGA IP can be evaluated with commercial VLSI CAD systems with high accuracy and reliability.

The importance of effective lower bound estimation (LBE) techniques is well established in high-level synthesis (HLS) since it allows more efficient exploration of the design space while providing other HLS tools with the capability of predicting the effect of specific tools on the design space. Much of the previous work has focused on LBE techniques that use very simple cost models which primarily focus on the functional unit resources. With the push toward submicron technologies, simple models that use functional unit resources alone are not accurate enough to allow effective design space exploration since the effects of storage and interconnect can indeed dominate the cost function. In this paper, we present an integrated approach aimed at predicting lower bounds on hardware resources needed to implement a behavioral description within a given amount of time. Our area cost model accounts for storage (register) and interconnect resources (buses) in addition to functional resources. Our timing model uses a finer granularity that permits the modeling of functional unit, register, and interconnect delays. Our approach is integrated because we consider the dependencies between the different types of resources as well as the ordering in which the resources are allocated. We tested our technique for functional unit, storage, and interconnect requirements on several high-level synthesis benchmarks, and observed near-optimal results. We believe that our comprehensive LBE approach can lead to better quality HLS solutions in less time, and we demonstrate this approach in our paper.

We propose a novel recycled field programmable gate array (FPGA) detection method based on with-in die (WID) variation modeling. Model parameters extracted by the WID modeling simply but accurately represent the process variation of each FPGA, and thus, by using the model parameters as feature vector, machine learning effectively classifies target FPGAs into fresh or aged. Through experiment on commercial circuit simulator, the proposed method achieves 99.6% feature vector size reduction per FPGA with showing 96.0% detection accuracy; while our silicon result using commercial FPGA demonstrates the model parameters have a good distance properties between fresh and aged.