Systolic Architecture for Computing the Discrete Fourier Transform on FPGAs

In this paper a novel coded multi-dimensional spreading technique using the Discrete Fourier Transform (DFT) is introduced. It exploits the DFT characteristic of spreading one symbol in one domain to all the symbols in the corresponding transform domain. Frequency domain channel estimation is performed at the receiver. The performance of a coded twodimensional (2D) DFT spreading communication system is investigated and simulation results are presented, using first a 2D DFT time-frequency system and then a 2D DFT space-frequency system. The proposed 2D DFT system shows good immunity to narrowband interference and impulse noise and exhibits a significant performance improvement when compared with a coded conventional OFDM system of equivalent size.

— Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. This paper presents rapid prototyping results of a bandpass filter as a sample analog circuit using our floating-gate based large-scale FPAA. A major source of parasitics introduced during the circuit mapping process is interconnect switches used for routing. Our goal is to obtain models of the mapped circuits that can be simulated using SPICE in order to observe the impact of interconnect parasitics on the relevant analog metrics. Our results indicate that the mapped analog circuits obtain desired responses even with interconnect parasitics, clearly demonstrating the practicality of our FPAA. I.

This paper proposes a 2D face recognition algorithm using phase-based correspondence matching. The phase information obtained from 2D DFT (Discrete Fourier Transform) of images contains important information of image representation. The phase-based image matching is successfully applied to sub-pixel image registration tasks for computer vision applications and image recognition tasks for biometric authentication applications. Hierarchical block matching using phase information, i.e, phase-based correspondence matching, can find the corresponding points on the input image from the reference points on the registered image with sub-pixel accuracy. For face recognition, the phase-based correspondence matching is useful for minute change of texture, such as facial expression change, illumination change, etc. Experimental evaluation using the CSU Face Identification Evaluation System with the FERET database demonstrates efficient recognition performance of the proposed algorithm compared with the conventional face recognition algorithms.

The Pietra-Ricci index detector (PRIDe) has been recently proposed as one of the simplest techniques for centralized, data-fusion cooperative spectrum sensing, attaining robustness against time-varying signal and noise levels, constant false alarm rate, and high detection power. In this paper, we propose the design and implementation of the PRIDe detector, targeting field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) solutions. Novel approaches are proposed for computing the PRIDe’s test statistic, including the absolute value of complex quantities, the complex multiplier-accumulator, and the spectrum occupancy decision. The absolute value operation, which is critical to the PRIDe test statistic computational cost, applies the coordinate rotation digital computer (CORDIC) algorithm as a low latency and resource-efficient option. Register transfer level (RTL) and Monte Carlo simulations show that the resulting ultra-low latency PRIDe detector architectures attain no performance loss with respect to floating-point simulations. One of the two proposed ASIC design versions of the PRIDe sensor occupies 34.9% lower area compared to the most area-efficient sensor reported in literature, whereas the other one is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5.7\times$</tex-math> </inline-formula> faster than the fastest state-of-the-art sensor. In a nutshell, the proposed detector architecture delivers the highest area and power efficiencies, considering the scaled values of area-time product (ATP) and power-delay product (PDP) metrics, in comparison to implementations reported to date.

In wireless communication, multiple receive-antennas are used with orthogonal frequency division multiplexing (OFDM) to improve the system capacity and performance. The discrete Fourier transform (DFT) plays an important part in such a system since the DFTs are required to be performed for the output of all those antennas separately. This paper presents area-time efficient systolic structures for one-dimensional (1-D) and two-dimensional (2-D) DFTs of general lengths. A low-complexity recursive algorithm based on Clenshaw’s recurrence relation is formulated for the computation of 1-D DFT. The proposed algorithm is used further to derive a linear systolic array for the DFT. The concurrency of computation has been enhanced and complexity is minimized by the proposed algorithm where an N −point DFT is computed via four inner-products of real-valued data of length ≈ (N/2). The proposed 1-D structure offers significantly lower latency, twice the throughput, and involves nearly the same area-time complexity of the corresponding existing structures. The proposed algorithm for 1-D DFT is extended further to obtain a 2-D systolic structure for the 2-D DFT without involving any transposition operation.

High-level synthesis assisted, low-latency, area- and power-optimized FPGA implementation of MUSIC algorithm for direction-of-arrival estimation

The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

This chapter presents the design and evaluation of template-based Coarse-Grained Reconfigurable Array (CGRA) generated accelerators that process Orthogonal Frequency-Division Multiplexing receiver blocks. The CGRA operates as a coprocessor with a Reduced Instruction-Set Computing (RISC) processor so that the overall system yields the benefits of general- and special-purpose processing. The accelerators are designed by crafting the CGRA template to the computational and communication requirements of the algorithms in an effort to minimize the resource utilization and power dissipation on the target Field Programmable Gate Array (FPGA) device. The performance of each CGRA is recorded in terms of the number of clock cycles and several multiple performance metrics. The power consumption is also estimated by simulating the postfit gate-level FPGA netlist of the accelerators.

In this paper, we implemented the Discrete Wavelet Transform (DWT) for signal noise reduction on a Field Programmable Gate Array (FPGA) device, and combined the DWT module with the audio codec on the Cyclone-II EP2C35F72C6 FPGA on the Altera DE2 board connected to the chip. The signal was denoised by applying the thresholding only to the detail part of the DWT result. The results reveal the efficiency of our system design

The Discrete Fourier transform (DFT) is an important tool in digital signal processing. In this paper, a novel approach to DFT is proposed. The computation of DFT is transformed to the computation of the first-order moments by the simple mathematical deductions. It is well known that the first-order moments can be computed efficiently using only additions. An efficient systolic array is designed to implement DFT. The comparison with the existing methods shows the advantages of our method. The approach is also applicable to DFT inverses.

Secure transmission of sensitive data over open networks is a challenge in the present scenario of digital signal transmissions. Especially in 2D image signals, the adjacent pixel correlation is high which makes it a challenge to encrypt or hide the information from being fraudulently interpreted. Optical signal processing is preferred for image encryption owing to its high speed parallel processing. Fractional transforms are used for the digital implementation of the optical processing due to the fact that fractional orders enable to analyze a time variant signal where each fractional order correspond to an arbitrary angle of rotation. In this work, we apply a fractional Fourier transform for double image encryption, as fractional orders provide randomness and serve as secret key. The complex outcome of transform becomes a limitation due to requirement of double memory for storage and transmission besides computational complexity. To overcome this issue, a reality preserving scheme is applied to obtain real output from transform. A piecewise nonlinear chaotic map is used to introduce chaotic blending in the double image data. The larger key space of PWNCA based blending offers yet another security layer to the optical transform based encryption. The simulation results give testimony to the acquired randomness in the encrypted data. The proposed scheme is quite sensitive to keys and is robust against potential attacks.

We propose a novel, lossless compression algorithm, based on the 2D Discrete Fast Fourier Transform, to approximate the Algorithmic (Kolmogorov) Complexity of Elementary Cellular Automata. Fast Fourier transforms are widely used in image compression but their lossy nature exclude them as viable candidates for Kolmogorov Complexity approximations. For the first time, we present a way to adapt fourier transforms for lossless image compression. The proposed method has a very strong Pearsons correlation to existing complexity metrics and we further establish its consistency as a complexity metric by confirming its measurements never exceed the complexity of nothingness and randomness (representing the lower and upper limits of complexity). Surprisingly, many of the other methods tested fail this simple sanity check. A final symmetry-based test also demonstrates our method’s superiority over existing lossless compression metrics. All complexity metrics tested, as well as the code used to generate and augment the original dataset, can be found in our github repository: ECA complexity metrics1.

Content-addressable memory (CAM) is a high-speed lookup memory, which searches the entire memory in parallel and provides address of the input search word. Internet of things (IoT) technology needs access control list filters, deployed using CAM, to reduce the flow of invalid data through the network. Field-programmable gate arrays (FPGAs) play an important role to provide the computational power to IoT nodes using ultra low power modern devices. CAMs are emulated in FPGAs using different memories, i.e., block RAM, distributed RAM, and flip-flops (FFs). FPGA-based CAMs have large power consumption due to the involvement of each CAM cell in parallel comparison. This work presents a bank-selective strategy for gate-based binary CAM on FPGA, which reduces the amount of comparisons and reduces power consumption on target FPGA device. For every input search key, only one bank is activated using gated-clock to compare the input key to corresponding stored rules. A sample of 512 x 36 of the proposed architecture with four banks is implemented on Xilinx Virtex-6 FPGA that consumes 42% less dynamic power compared to the best available CAM designs. Hardware resources of the proposed CAM design on target FPGA is reduced in terms of slice registers (SRs) and lookup tables (LUTs) by 7.9% and 8.8%, respectively, compared with the latest prior work.

In todayýs deep-submicron designs, the interconnect delays contribute an increasing part to the overall performance of an implementation. Particularly when targeting field programmable gate arrays (FPGAs), interconnect delays are crucial, since they can easily vary by orders of magnitude. Many existing performance-directed retiming methods use simple delay models which either neglect routing delays or use inaccurate delay estimations. In this paper, we propose a retiming approach which overcomes the problem of inaccurate delay models. Our retiming technique uses delay information extracted from a fully placed and routed design and takes account of register timing requirements. By applying physical constraints, we ensure that the delay information remains valid during retiming. In our experiments, we achieved up to 27% performance improvement.

High Range Resolution (HRR) -based Automatic Target Recognition (ATR) has attracted increasing attention due to a number of potential advantages over alternative radar techniques in moving target identification. Most current HRR-based ATR studies have been conducted using 1D HRR signatures. However, these 1D HRR signatures are generally plagued by scintillation effects, and thus demonstrate highly irregular behavior that dramatically degrades the performance and robustness of algorithms based on these signatures. In order to circumvent this difficulty, an alternative HRR radar data representation and processing technique is presented in this paper. This technique models and extracts the target characteristics directly, based on the 2D HRR raw data. In this paper, we first derive a general, but complex HRR radar model, and then simplify this model by instantiating a set of real-world radar and target parameters for the model. This simplification process produces two HRR radar models with different degrees of simplicity. After establishing this set of models, the typical HRR data processes, such as feature extraction and clutter suppression, are reduced to one problem, which is model-parameter estimation. Based upon the most simplified HRR model we proposed, we devise two model- parameter estimation algorithms. One is a scatterer extraction algorithm based on available 1D Parameter Estimation (1DPE), while the other is based on 2D discrete Fourier Transform (2DFT). In order to examine the performance of these two algorithms a set of simulations are conducted. The experimental results are presented, and the performance comparison between 1DPE and 2DFT is presented.