Performance of multi‐tasking and synchronization mechanisms in the programming language SR

Process-oriented design and implementation of concurrent systems has important benefits. However, the inherent complexity of concurrent processes’ communication imposes challenges such as verifying consistency between the process-oriented design and implementation of a concurrent system. To deal with such a challenge, we use Galois connections, Failures and Category Theory to construct a formal framework for designing, implementing, analyzing and verifying consistency of concurrent systems. For the purpose of illustrating the framework, a running concurrent system is designed by Communicating Sequential Processes, implemented by a process-oriented programming language Erasmus.

Using Failures and Category Theory to Verify Process Communications between Design and Implementation of Concurrent Systems

The specification and implementation of a class of concurrent systems is investigated in this paper using PARLOG as the implementation language, guided by specifications in CCS. This class of systems is restricted to an illustrative subset, including buffers and queues. A comparison is made between the computational models of concurrency that are expressed by each language. Illustrative programs are given which highlight the differences in operational behaviour between programs in the two languages. We investigate the ways in which equivalences in CCS programs may be used to compare PARLOG programs, and the areas of PARLOG programming which are not covered by this comparison. The advantages and disadvantages of CCS compared with PARLOG as a ‘specification-implementation’ language are discussed.

The lack of formalism and rigor in existing multi-agents models often leads to ambiguities and different interpretations. Those weaknesses combined with the inherent complexity of multi-agents systems generate many problems in their development process. Using formal notations to specify multi-agents systems’ behavior makes it possible to produce precise description. This also offers a better support to their verification and validation process. The Maude language, based on rewriting logic, presents a rich notation supporting formal specification and implementation of concurrent systems. In this paper, we demonstrate the feasibility and the interest of formalizing the behavior of DIMA model’s agents with the Maude language. The elaborated formal approach captures the inherent aspects of a DIMA model. The generated Maude descriptions have been validated using the platform supporting this language. Moreover, the proposed approach is generic and extensible. It offers, in particular, the advantage of being applicable to all multi-agents systems based on DIMA architecture and presents interesting extension possibilities.

In this paper, we present a novel Web-based multi-user Virtual Reality system for a virtual tour of remote places. The proposed system supports not only 360-degree images but also live 360-degree videos. In addition, a synchronization mechanism is proposed to allow multiple users to participate in a virtual tour at the same time. A subjective experiment demonstrates that the proposed system can provide a high level of spatial presence and involvement to users.

Concurrency has been with us almost from the beginning of computing. Managing and programming for concurrency is a difficult problem and various solutions have been suggested over the years. Debates on message passing vs. remote procedure call, synchronous vs. asynchronous message passing, bounded vs. unbounded buffers, active vs. passive objects etc. still continue. No solution is entirely satisfactory. Concurrent programming usually depends heavily on the nature of the problem at hand and the architecture of the target machine.

18 - C++ Concurrency Support

The paper considers the problem of ensuring trouble-free operation of technological equipment operating in automatic mode, using the example of a pneumatic cylinder assembly line. It is shown that with the increasing complexity of automated systems, increasing speed and increasing the number of operations performed without the participation of the operator, the requirements for equipment reliability, accuracy of mutual positioning of elements and timely detection of emergency and pre-emergency states are significantly increasing. Particular attention is paid to operations of precision connection of critical structural elements, which are characterized by errors in the form of misalignment, skew of axes and inconsistency of spatial orientation of parts, which can lead to a decrease in the resource of mechanisms or equipment failure. An approach to organizing test and step-by-step modes of operation of an automatic control system is proposed, which allows for phased control of the execution of technological operations, identification of positioning errors and failures of actuators without the system going into emergency mode. The principles of constructing an asynchronous control machine using typical pneumatic cylinder control modules, as well as mechanisms for time synchronization of control and feedback signals, are considered. The structure of a typical control module is presented, which ensures coordination of external asynchronous signals with internal clock synchronization and implements control of the permissible time for performing technological operations. The proposed technical and algorithmic solutions increase the reliability of automatic assembly lines, ensure timely detection of failures, reduce the likelihood of emergency situations and create the prerequisites for the implementation of intelligent diagnostic and protection systems for modern technological equipment.

Per-core local (scratchpad) memories allow direct inter-core communication, with latency and energy advantages over coherent cache-based communication, especially as CMP architectures become more distributed. We have designed cache-integrated network interfaces (NIs), appropriate for scalable multicores, that combine the best of two worlds the flexibility of caches and the efficiency of scratchpad memories: on-chip SRAM is configurably shared among caching, scratchpad, and virtualized NI functions. This paper presents our architecture, which provides local and remote scratchpad access, to either individual words or multi-word blocks through RDMA copy. Furthermore, we introduce event responses, as a mechanism for software configurable synchronization primitives. We present three event response mechanisms that expose NI functionality to software, for multiword transfer initiation, memory barriers for explicitly-selected accesses of arbitrary size, and multi-party synchronization queues. We implemented these mechanisms in a four-core FPGA prototype, and evaluated the on-chip communication performance on the prototype as well as on a CMP simulator with up to 128 cores. We demonstrate efficient synchronization, low-overhead communication, and amortized-overhead bulk transfers, which allow parallelization gains for fine-grain tasks, and efficient exploitation of the hardware bandwidth.

This paper discusses formal specification and verification of the synchronisation classes of the Java API. In many verification systems for concurrent programs, synchronisation is treated as a primitive operation. As a result, verification rules for synchronisation are hard-coded in the logic, and not verified. These rules describe the concrete semantics of the given synchronisation primitive, and manage how resources are protected by synchronisation. In contrast, this paper describes several synchronisation primitives at the specification level, by specifying the behaviour of synchronisation routines from the Java API at method level using permission-based Separation Logic. This gives a generalised, high-level, and easily extendable approach to formalisation of arbitrary synchronisation mechanisms, which allows for modular treatment of synchronisation in verification. Notably, our approach does not only apply to locks, but also to other synchronisation mechanisms such as semaphores and latches that we also discuss. Finally, we used the verification tool that we are developing and successfully verified (so far simplified) implementations of all presented synchronisers, the paper discusses the verification of one of them.

It is expected that the first exascale supercomputer will be deployed within the next 10 years, but which programming model will allow easy development and yet scalable and efficient programs is still not known. One of the programming models considered to be feasible is the so-called partitioned global address space~(PGAS) model, which allows easy development by providing one common memory address space across all cluster nodes. In this paper we compare remote memory access and memory consistency of current PGAS programming languages and describe how synchronization can generated unneeded network transfers. We furthermore introduce our variation of the PGAS model that allows for implicit fine-grained pair-wise synchronization among the nodes. Efficient and easy to use synchronization is necessary to keep all the processors of upcoming supercomputers busy. We furthermore offer easy deployment of RDMA transfers and use communication algorithms commonly used in MPI collective operations, but lift the requirement of the operations to be collective. Our model is based on single assignment variables and uses a data-flow like synchronization mechanism. Reading uninitialized variables results in the reading thread to be blocked until data are made available by another thread. That way synchronization is done implicitly when data are read. Broadcast, scatter and gather are modeled based on data distribution among the nodes, whereas for reduction and scan we follow a combining PRAM approach of having multiple threads write to the same memory location. We discuss both a Gaus-Seidel stencil and bitonic sort in our model. We implemented a proof-of-concept library showing the usability and scalability of the model. With this library the Gaus-Seidel stencil scaled well in initial experiments on an 8-node machine.

A fully abstract model for the exchange of information in multi-agent systems

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ultimately limited by the performance of the underlying cache coherence protocol. This paper studies how hardware support for message passing can improve synchronization performance. Considering the ubiquitous problem of mutual exclusion, we adapt two state-of-the-art solutions used on shared-memory processors, namely the server approach and the combining approach, to leverage the potential of hardware message passing. We propose HybComb, a novel combining algorithm that uses both message passing and shared memory features of emerging hybrid processors. We also introduce MP-Server, a straightforward adaptation of the server approach to hardware message passing. Evaluation on Tilera's TILE-Gx processor shows that MP-Server can execute contended critical sections with unprecedented throughput, as stalls related to cache coherence are removed from the critical path. HybComb can achieve comparable performance, while avoiding the need to dedicate server cores. Consequently, our queue and stack implementations, based on MP-Server and HybComb, largely outperform their most efficient pure-shared-memory counterparts.

This article describes the design, implementation and characterization of a novel optical tweezer system. The system utilizes a deformable mirror, wavefront sensor and controller to manipulate an optically trapped micro-particle within a small chamber. This method for optical trapping employs technology adopted from astronomical instrumentation; in particular, adaptive optics. A deformable mirror is employed to control the wavefront phase of a laser beam before it is imaged into a chamber by a high numerical aperture microscope objective lens. The wavefront phase is measured by a Shack–Hartman wavefront sensor and the particle's position monitored by a video camera. The goals of the work presented here are to trap particles ranging in size from 1 μm to 10 μm; create a suitable controller for moving trapped particles in three dimensions; image the trapped particle; determine the prototype system's performance specifications; and determine the trap stiffness.

CSP# is a formal modeling language that emphasizes the design of communication in concurrent systems. PAT framework provides a model checking environment for the simulation and verification of CSP# models. Although the desired properties can be formally verified at the design level, it is not always straightforward to ensure the correctness of the system's implementation conforms to the behaviors of the formal design model. To avoid human error and enhance productivity, it would be beneficial to have a tool support to automatically generate the executable programs from their corresponding formal models. In this paper, we propose such a solution for translating verified CSP# models into C# programs in the PAT framework. We encoded the CSP# operators in a C# library-PAT.Runtime, where the event synchronization is based on the Monitor class in C#. The precondition and choice layers are built on top of the CSP event synchronization to support language-specific features. We further developed a code generation tool to automatically transform CSP# models into multi-threaded C# programs. We proved that the generated C# program and original CSP# model are equivalent on the trace semantics. This equivalence guarantees that the verified properties of the CSP# models are preserved in the generated C# programs. Furthermore, based on the existing implementation of choice operator, we improved the synchronization mechanism by pruning the unnecessary communications among the choice operators. The experiment results showed that the improved mechanism notably outperforms the standard JCSP library.