Pipelined MIPS Simulation: A plug-in to MARS simulator for supporting pipeline simulation and branch prediction

This research adopts the VHDL (Very high speed IC Hardware Description Language) design of a direct mapped cache controller for a pipelined MIPS (Microprocessor without Interlocked Pipeline Stages) processor. In this design, the instruction cache and data cache are separated and located in the CPU (Central Processing Unit) core. Write back policy is used while no replacement algorithm is required. After completing the cache controller design, it is combined with a pipelined MIPS processor and used in programs execution. These designs are synthesized using (Xilinx ISE Design Suite 13.4) and simulated using (Xilinx ISim simulator).

This paper presents the design and development of a new plug-in to the well-known MIPS Assembler and Runtime Simulator (MARS). The MIPS processor is a reduced instruction set computer (RISC), while the MARS simulator is a lightweight interactive development environment for programming in MIPS assembly language, intended for educational-level use. The proposed plug-in, called MIPS X-Ray, provides a dynamic dataflow diagram, which allows MARS users to visualize the execution of operations internally to the MIPS architecture. By using the proposed plug-in, MARS users can better analyze the developed assembly codes, improving their understanding about the MIPS processor, as well as their debugging capabilities.

There is wide agreement that one of the most important impediments to the performance of current and future pipelined superscalar processors is the presence of conditional branches in the instruction stream. Speculative execution seems to be one solution of choice to the branch problem, but speculative work is discarded if a branch is mispredicted. Therefore, we need a very accurate branch predictor; 95% accuracy is not good enough. This paper proposes branch classification to help improve the accuracy of branch predictors. Branch classification allows an individual branch instruction to be associated with the branch predictor best suited to predict its direction. Using this approach, a hybrid branch predictor can be constructed such that each component branch predictor predicts those branches for which it is best suited. This paper suggests one classification scheme, analyzes several branch predictors, and proposes a hybrid branch predictor that achieves higher prediction accuracy than any branch predictor previously reported in the literature.

The design of the modern, enterprise-class IBM z15 branch predictor is described. Implemented as a multi-level look-ahead structure, the branch predictor is capable of predicting branch direction and target addresses, augmented with multiple auxiliary direction, target, and power predictors. Predictions are made asynchronously, and later integrated into the processor pipeline. The design is optimized for the unique workloads executed on these enterprise-class systems, including compute intensive and both large instruction and data footprint workloads. This paper highlights the major operations and functions of the IBM z15 branch predictor, including its pipeline, prediction structures and verification methodology. Explanations as to how the design matured to its current state are also provided.

The need for modern processors is based on fast and precise branch predictors to improve the execution of instructions in the pipeline. In a parallel processor, the pipeline cannot execute the conditional instructions with the next clock cycle, leading to a pipeline stall. To address this issue, this paper suggests a variety of branch prediction techniques for improving the execution speed of conditional instructions. Firstly, a simple branch prediction and a dynamic branch prediction are applied to the trace files using saturating counters. Among these two, dynamic branch prediction provides better results by enhancing the accuracy rate of 2.01% than the static branch prediction. Further, the perceptron branch predictor predicts the implementation by using a table of perceptron and train function. This prediction scheme reduces the difficulties in dynamic branch predictor schemes such as reduces the complexity in history length table and improves the accuracy rate by 5.36%. For accuracy, a novel model based on global perceptron branch predictor is developed, which uses both global and per branch information. Trace-driven simulations have been performed by varying the range of hardware budget, traces file size, and the length of history register to increase the accuracy rate of each branch prediction technique. The obtained results suggest that the proposed global perceptron branch predictor provides an increased accuracy rate of 10.47% at 4 kb hardware budget and 8.06% at 4-bit history length than the perceptron branch predictor.

Pipeline image processing systems are increasingly being used in industrial vision systems, in particular in manufacture visual inspection. There has been little work done in the study of the appropriate software environment for rapid program development for these machines. In this paper, an approach to improve software programmability of these systems was proposed. The software features reflecting the hardware capabilities as well as the nature of image processing applications were discussed. A preprocessor was developed to support the high level programming environment and the abstract data structures. The preprocessor also analyzed the image processing tasks expressed as expressions and generate the hardware setup and connections necessary for multipass operations through the pipeline processor. A prototype implementation of the preprocessor and an example were also discussed.

As fields like AI and robotics continue to expand, the demand for processors that are both powerful and energy-efficient is growing. This imposes the need for the development of such processors at a large scale and at a faster rate, which is possible through open-source development. While the current computing industry is dominated by proprietary technologies and licensed architectures, open-source hardware is rapidly gaining popularity across all industry segments, from high-performance computing to edge-IoT applications.This paper presents the design and FPGA implementation of a 32-bit five-stage pipelined processor core based on the RISC-V open-source Instruction Set Architecture (ISA). The proposed design presents a simple implementation of the RISC-V core, incorporating a 2-bit branch predictor. This makes it easier for beginners to understand the fundamental architecture of a pipelined RISC processor and branch predictors. Additionally, the design has considerable potential for future upgrades. The core is developed using SystemVerilog and has been tested through simulations in Verilator and Xsim, as well as by deploying it on a Basys3 FPGA board.

Programming is an important course for any IT or engineering-related course. However, previous research shows that students face difficulties in learning programming due to its abstract concepts. This study aims to evaluate the acceptance of a developed Integrated Development Environment (IDE), namely C-SOLVIS which is a web-based application that specifically intends to facilitate the teaching and learning of the C programming fundamentals in Malaysian tertiary education. The C-SOLVIS integrates problem-solving into a program development environment for the C language. The goal is to guide the users in problem-solving and help them write C programs based on problem-solving algorithms. The Rapid Application Development (RAD) Model was employed in the C-SOLVIS development process. Based on this model, the requirement planning phase was carried out through the triangulation technique by applying qualitative approaches comprising a literature review supported by semi-structured interviews, document reviews, and content validation by expert programming lecturers. Subsequently, the design of the application was accomplished through the iterative prototyping process which was then followed by the application construction. Then, the C-SOLVIS is deployed to be used by several programming lecturers to evaluate its usability by adopting a quantitative method using the System Usability Scale (SUS) questionnaire. The study has discovered several suitable techniques and designs for the problem-solving and program development environment. For the problem-solving environment, the Computational Thinking (CT) concepts were applied which were supported by the Input-Process-Output (IPO) Model through Scientific Instructions and Inquiries. Meanwhile, the program development environment was designed and developed based on frame-based programming using a set of developed Code Patterns. The C-SOLVIS evaluation using the SUS instrument has yielded a SUS mean score of 86.07. This score is interpreted by SUS as an A grade that indicates C-SOLVIS as a highly usable application and thus is accepted for C programming learning. Hence, the development process of the C-SOLVIS can be used as a guideline for educational software development, especially in the field of programming education.

When provided with the support of proper development and maintenance tools, programmers are more likely to work efficiently and produce high-quality software [1,2]. A mature and professional Integrated Development Environment (IDE) provides the required tools in an integrated manner and allows those tools to be easily adapted for use in new contexts as well [3]. Providing these capabilities for agent-oriented programming (AOP) is not trivial. Specific features of agents like decision cycles, rule-based evaluations, mental states, external environments, and embedded knowledge representation (KR) technologies pose specific challenges to the design and development of an IDE for AOP. These challenges significantly differ from object-oriented or functional programming for example, as those paradigms do not (inherently) deal with for instance distributed execution, database inspection, and logic inference. In this paper, we present a mature and professional IDE for the multiagent programming language GOAL [4]. In contrast to other AOP development environments, our approach is novel, as we fully integrate all agent and agent-environment development tools within one environment. Other AOP development environments are generally composed of several standalone tools [5]. For instance, running or debugging an agent after editing its program code is usually performed in a separate application (pop-up).

A conditional branch predictor based on weightless neural networks

Embedded systems are often subject to constraints that require determinism to ensure that task deadlines are met. Such systems are referred to as real-time systems. Schedulability analysis provides a firm basis to ensure that tasks meet their deadlines for which knowledge of worst-case execution time (WCET) bounds is a critical piece of information. Static timing analysis techniques are used to derive these WCET bounds. A limiting factor for designing realtime systems is the class of processors that can be used. Typically, modern, complex processor pipelines cannot be used in real-time systems design. Contemporary processors with their advanced architectural features, such as out-of-order execution, branch prediction, speculation, prefetching, etc., cannot be statically analyzed to obtain tight WCET bounds for tasks. This is caused by the non-determinism of these features, which surfaces in full only at runtime. In this paper, we introduce a new paradigm to perform timing analysis of tasks for real-time systems running on modern processor architectures. We propose minor enhancements to the processor architecture to enable this process. These features, on interaction with software modules, are able to obtain tight, accurate timing analysis results for modern processors. We also briefly present analysis techniques that, combined with our timing analysis methods, reduce the complexity of worst-case estimations for loops. To the best of our knowledge, this method of constant interactions between hardware and software to calculate WCET bounds for out-of-order processors is the first of its kind.

This paper demonstrates the modeling and deductive verification of out-of-order microprocessors of varying complexities using a logic of Counter Arithmetic with Lambda Expressions and Uninterpreted Functions (CLU). The microprocessors support combinations of out-of-order instruction execution, superscalar operation, branch prediction, execute and memory exceptions, and load-store buffering. We illustrate that the logic is expressive enough to model components found in modern processors. The paper describes the challenges in modeling and verification with the addition of different design features. The paper demonstrates the effective use of automatic decision procedure to reduce the amount of manual guidance required in discharging most proof obligations in the verification. Unlike previous methods, the verification scales well for superscalar processors with wide dispatch and retirement widths.

We describe some of the novel aspects and motivations behind the design and implementation of the Ciao multiparadigm programming system. An important aspect of Ciao is that it provides the programmer with a large number of useful features from different programming paradigms and styles, and that the use of each of these features can be turned on and off at will for each program module. Thus, a given module may be using e.g. higher order functions and constraints, while another module may be using objects, predicates, and concurrency. Furthermore, the language is designed to be extensible in a simple and modular way. Another important aspect of Ciao is its programming environment, which provides a powerful preprocessor (with an associated assertion language) capable of statically finding non-trivial bugs, verifying that programs comply with specifications, and performing many types of program optimizations. Such optimizations produce code that is highly competitive with other dynamic languages or, when the highest levels of optimization are used, even that of static languages, all while retaining the interactive development environment of a dynamic language. The environment also includes a powerful auto-documenter. The paper provides an informal overview of the language and program development environment. It aims at illustrating the design philosophy rather than at being exhaustive, which would be impossible in the format of a paper, pointing instead to the existing literature on the system.

Research on IPSE architectures has discussed the benefits of a centralized repository at some length. Such a repository has to not only offer enhanced data management services but also provide for mechanisms to assist in the building and use of tools. Tools impose a special set of requirements because of the manner in which they are specified and reused. The area of programming and software development environments is rich in proposals regarding tool specification and integration. The demands that these proposals place on an IPSE database are discussed. >

User-defined functions (UDFs) facilitate the execution of analytics pipelines inside the database. They provide many advantages over traditional methods, such as close-to-data execution and automatic parallelization. However, the standard workflow for developing and debugging UDFs does not allow developers to use their regular toolchains and Integrated Development Environments (IDEs). As a result, writing functional UDFs is challenging. In this demo, we present the devUDF, a plugin to the PyCharm IDE that allows developers to develop and debug their MonetDB/Python UDFs directly from within the IDE.