Plugging Versus Logging

ZTL: A block layer ZNS driver

Due to high access performance and price-per-byte considerations, flash memory has been recommended for use as a mid-tier cache in a multi-tier storage system. However, previous studies related to flash-based mid-tier caching only considered the indirect use of flash memory via a flash translation layer, which causes expensive flash-based cache maintenance. This paper identifies the weaknesses of such indirect methods, with a focus on the cold-page migration problem. As improvements, we propose two novel approaches, an indirect approach called LPD (logical page drop) and a native approach called NFA (native flash access). The basic idea is to drop cold pages proactively so that the garbage collection overhead can be minimized. Our experiments demonstrate that both approaches, especially the native one, effectively improve the use of flash memory in the mid-tier cache. NFA reduces the number of garbage collections and block erasures by up to a factor of five and improves the mid-tier throughput by up to 66%.

The internal copy (IC) is a simple, yet powerful in-storage processing function, which changes the locations of data blocks without invoking any data transfer between the host and storage. Owing to the out-of-place update constraint of flash memory, solid-state disks (SSDs) employ a flash translation layer (FTL) to manage the logical-to-physical address translation. By leveraging the address indirection feature of SSDs, the IC can be processed only by remapping flash pages to new logical addresses without flash read/write operations. In the existing studies on remap-based IC, SSDs were assumed to have only a single FTL instance. However, recent large-capacity SSDs adopt an arrayed architecture including multiple FTL controllers, where each controller runs an FTL instance to manage its own partitioned address space. For the arrayed SSDs, inter-partition copy requests cannot be handled by address remapping because each partition is managed by a different FTL instance. In this study, we propose an inter-partition remap technique for IC-enabled arrayed SSDs. Additionally, we present the block allocation technique to minimize the number of inter-partition copy requests. Our proposed IC techniques were implemented on an actual arrayed SSD, and showed significant performance improvements compared to the previous remap techniques in several use cases.

Flash Translation Layer (FTL) is a key technology in a Solid–State Disk (SSD) system to manage the data transfer. Different mapping granularity in FTL will cause a change in the read/write performance and the size of mapping table. For the scenario that big capacity storage needs to hold high performance, on the basis of former mapping algorithms, this paper design a mapping method based on grouping pages granularity, and a SSD system architecture based on the parallelism of flash chip array. Besides, considering the features of the mapping method, we implement the corresponding wear-leveling algorithm and garbage collection algorithm. By computer simulation verifying, under four kinds of workload, the method proposed in this paper can decrease the size of mapping table and keep excellent read/write performance at the same time.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Garbage collection algorithms that do not require tagging of data have been around since the early days of LISP. With the emergence of strongly-typed languages that require heap allocation, interest in tag-free garbage collection has increased. Several papers published recently describe methods for performing tag-free copying garbage collection by retaining compile-time type information at run time. However, all of these algorithms have the “stop and collect” property, in which program execution is suspended for a significant amount of time during garbage collection. For many programs an incremental garbage collection method, in which the garbage collection overhead is spread evenly throughout the computation, is desirable.

FTL (Flash Translation Layer) is a memory block controller that manages the challenges of a data storage system based on flash memory technology. The design of internal parallelism in MLC-based SSDs with virtual blocks resulted in various challenges and due to the physical structure of flash memory cells based on MLC technology, it is possible to write a new page in a data block at the address after the last page is written. In parallel-based SSD design based on virtual blocks, some writes create unusable pages at the memory space, and these created holes reduce memory efficiency; consequently, it reduces the life-time of memory blocks by creating more operations, and accelerates garbage collection and merging operations. The proposed FTL offers three steps to address this constraint. Firstly, an idea was proposed to prevent costly transitions and to distribute data more evenly at memory blocks (wear leveling). Secondly, the unused holes created in virtual blocks became much fewer resulting in increased utilization of memory space. At last, a policy was proposed to prevent update blocks (log blocks) from being blocked and to postpone the merging and garbage collection by which the memory lifetime increases significantly. Simulation results showed that the number of unused erased pages and the number of extra write operations decreased up to 23% and 17%, respectively. In addition, the number of invalid released pages increased up to 21% in the proposed FTL, and the speed of I/O executions to 3%.

In this paper, we propose PGIS, a parallelism and garbage collection aware I/O Scheduler, which identifies the hot data based on trace characteristics to exploit the channel level internal parallelism of flash-based storage systems. PGIS not only fully exploits abundant channel resource in the SSD, but also it introduces a hot data identification mechanism to reduce the garbage collection overhead. By dispatching hot read data to different channel, the channel level internal parallelism is fully exploited. By dispatching hot write data to the same physical block, the garbage collection overhead has been alleviated. The experiment results show that compared with existing I/O schedulers, PGIS improves the response time and garbage collection performance significantly. Consequently, PGIS reduces the garbage collection overhead up to 30.9%, while exploiting channel level internal parallelism.

Recent consumer devices such as smartphones, smart TVs and tablet PCs adopt NAND flash memory as storage device due to its advantages of small size, reliability, low power consumption, and high performance. The unique characteristics of NAND flash memory require an additional software layer, called flash translation layer (FTL), between traditional file systems and flash memory. In order to reduce the garbage collection cost, FTLs generally try to separate hot and cold data. Previous hot and cold separation techniques monitor the storage access patterns within storage device, or exploit file system hints from host system. This paper proposes a novel clustered page-level mapping, called CPM, which can separate hot and cold data efficiently by allocating different flash memory block groups to different logical address regions. CPM can reduce the FTL map loading overhead during garbage collection and it does not require any high-cost monitoring overhead or host hint. This paper also proposes a K-associative version of CPM, called K-CPM, which allows different logical address regions to share a physical block group in order to achieve high block utilizations. Experimental results show that CPM improves the storage I/O performance by about 54% compared with a previous page-level mapping FTL, and K-CPM further improves the performance by about 19.4% compared with CPM.

Flash translation layer (FTL) is a firmware embedded in NAND-based block devices. It hides unique characteristics of NAND flash memory and emulates a standard block device interface. The overall performance of NAND-based block devices is mainly determined by the efficiency of the FTL schemes, and thus, it is important to evaluate the FTL performance to design high-speed NAND-based block devices, which is a main objective of this work. Whereas most previous works have not considered device utilization from a FTL perspective and have fixed the over-provisioning factor, this work evaluates their performance varying device utilization and allows unused space to be used as over-provision area. A trace-driven simulation shows that device utilization significantly influences on FTL’s performance. Especially, the page mapping FTL is vulnerable against high utilization, even though it delivers a good performance at low utilization. In contrast, the fully associative sector translation (FAST) FTL is less sensitive to the utilization and delivers a competing performance. It even outperforms the page mapping FTL at high utilization.

MaCACH: An adaptive cache-aware hybrid FTL mapping scheme using feedback control for efficient page-mapped space management

A large write amplification ratio degrades the program/erase cycles (P/Es) of NAND Flashes and reduces the endurance and performance of solid state disks (SSDs). The lack of a practical way to measure write amplification for SSDs motivates us to propose a novel measuring method called RB-Explorer at the SSD level rather than the NAND Flash level. The goal of RB-Explorer is two-fold: (1) to accurately measure the write amplification of SSDs to quantify SSD endurance and (2) to study the impacts of I/O techniques on write amplification of SSDs. RB-Explorer incorporates a Ready/Busy (R/B) signal of one of the NAND Flashes in an SSD in a proposed write amplification model for SSDs with four full-parallelism levels (i.e., the channel, chip, die, and plane levels). RB-Explorer takes two steps toward measuring write amplification. First, RB-Explorer quantifies the number of page programs using the low R/B signal level, the duration of which varies with the different operation (i.e., read, program, and erase) in NAND Flash. Second, RB-Explorer measures data volume written to NAND Flashes by considering parallelisms at four levels. Data volume written to a die in a NAND Flash is obtained as a product of the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX"> ${\rm N_{p}}$</tex><mathgraphic fileref="sun-ieq1-2308207.gif" graphicformat="GIF"/></formula> of programs and page size <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm P_{a}}$</tex> <mathgraphic fileref="sun-ieq2-2308207.gif" graphicformat="GIF"/></formula> . Given the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq3-2308207.gif" graphicformat="GIF"/></formula> of channels, the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{chip}}$</tex> <mathgraphic fileref="sun-ieq4-2308207.gif" graphicformat="GIF"/></formula> of chips per channel, and the number <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{die}}$</tex> <mathgraphic fileref="sun-ieq5-2308207.gif" graphicformat="GIF"/></formula> of dies per chip, one can obtain the data volume written to NAND Flashes as a product of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{p}}, {\rm P_{a}}, {\rm N_{die}}, {\rm N_{chip}}$</tex><mathgraphic fileref="sun-ieq6-2308207.gif" graphicformat="GIF"/></formula> , and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${\rm N_{channel}}$</tex> <mathgraphic fileref="sun-ieq7-2308207.gif" graphicformat="GIF"/></formula> . RB-Explorer is applied to analyzing write amplification ratios of SSDs to track SSD endurance. Furthermore, we implement a real-world SSD (i.e., SSD-v) and employ a fine-tuned SSD simulator (i.e., SSDsim) to validate the accuracy of RB-Explorer. Our experimental results show that RB-Explorer improves on the accuracy of SSDsim—the state-of-the-art SSD simulator—in most tested cases. We conduct a series of measurements using micro-benchmarks and I/O traces to demonstrate how RB-Explorer may be applied to investigate SSDs.

An associative model to minimize matching and backtracking overhead in logic programs with large knowledge bases

The poor performance of random writes has been a cause of major concern which needs to be addressed to better utilize the potential of flash in enterprise-scale environments. We examine one of the important causes of this poor performance: the design of the flash translation layer (FTL) which performs the virtual-to-physical address translations and hides the erase-before-write characteristics of flash. We propose a complete paradigm shift in the design of the core FTL engine from the existing techniques with our Demand-Based Flash Translation Layer (DFTL) which selectively caches page- level address mappings. Our experimental evaluation using FlashSim with realistic enterprise-scale workloads endorses the utility of DFTL in enterprise-scale storage systems by demonstrating: 1) improved performance, 2) reduced garbage collection overhead and 3) better overload behavior compared with hybrid FTL schemes which are the most popular implementation methods. For example, a predominantly random-write dominant I/O trace from an OLTP application running at a large financial institution shows a 78% improvement in average response time (due to a 3-fold reduction in operations of the garbage collector), compared with the hybrid FTL scheme. Even for the well-known read-dominant TPC-H benchmark, for which DFTL introduces additional overheads, we improve system response time by 56%. Moreover, interestingly, when write-back cache on DFTL-based SSD is enabled, DFTL even outperforms the page-based FTL scheme, improving their response time by 72% in Financial trace.

Flash memory has been widely used in various embedded computing systems and portable devices in recent years because of its small size, shock-resistance, low-power consumption and non-volatile properties. To hide the disadvantages of flash memory such as out-of-place update, a flash translation layer (FTL) is usually used for providing transparent block-device emulation. But when index structures are implemented over FTL, intensive overwrite operations caused by record inserting, deleting, modifying and index reorganizing could not only degrade the performance significantly but also reduce the life of flash memory. To address the problem, BFTL and IBSF are proposed. However, neither of them could avoid the loss of records and incompatibilities when system crash occurs. In this paper, a reliable B-tree implementation called RBFTL is presented for flash-memory storage systems. It is placed between the application layer and FTL. RBFTL could minimize the loss of data and eliminate incompatibilities effectively and efficiently when system crashes. The experimental results also show that RBFTL yields a better performance than FTL.