Post‐Mapping Transformations for Low‐Power Synthesis

Article Free Access Share on Circuit delay models and their exact computation using Timed Boolean Functions Authors: William K. C. Lam View Profile , Robert K. Brayton View Profile , Alberto L. Sangiovanni-Vincentelli View Profile Authors Info & Claims DAC '93: Proceedings of the 30th international Design Automation ConferenceJuly 1993 Pages 128–134https://doi.org/10.1145/157485.164625Published:01 July 1993Publication History 18citation300DownloadsMetricsTotal Citations18Total Downloads300Last 12 Months7Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Presents a covering technique for optimizing the average-case delay of asynchronous burst-mode control circuits during technology mapping. The specification and the NAND-decomposed unmapped network of these circuits are first preprocessed using stochastic techniques to determine the relative frequency of occurrence of each state transition and the corresponding sensitized paths through the NAND-decomposed network. We minimize the sum of the implementation's cycle times of the state transitions, weighted by their relative frequencies, thereby optimizing for average-case performance. Our results demonstrate that a 10-15% improvement in performance con be achieved with run-times comparable to synchronous techniques.

Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. Table of Contents: Introduction to Asynchronous Logic / Overview of NULL Convention Logic (NCL) / Combinational NCL Circuit Design / Sequential NCL Circuit Design / NCL Throughput Optimization / Low-Power NCL Design / Comprehensive NCL Design Example

We consider the problem of circuit partitioning for multiple-chip implementations. One motivation for studying this problem is the current need for good partitioning tools for implementing a circuit on multiple field programmable gate array (FPGA) chips. We allow duplication of logic gates as it could be used to reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the nonoptimality occurs, and we show that the condition rarely occurs in practice. We tested our algorithm on a set of benchmark circuits, and consistently obtained optimal or near-optimal delays.

We consider the problem of circuit partitioning for multiple-chip implementation. One motivation for studying this problem is the current needs of good partitioning tools for implementing a circuit on multiple FPGA chips. We allow duplication of logic gates as if would reduce circuit delay. Circuit partitioning with duplication of logic gates is also called circuit clustering. In this paper, we present a circuit clustering algorithm that minimizes circuit delay subject to both area and pin constraints on each chip, using the general delay model. We develop a repeated network cut technique for finding a cluster that is bounded by both area and pin constraints. Our algorithm achieves optimal delay under either the area constraint only or the pin constraint only. Under both area and pin constraints, our algorithm achieves optimal delay in most cases. We outline the condition under which the non-optimality occurs and show that the condition occurs rarely in practice. We tested our algorithm on a set of benchmark circuits and consistently obtained optimal or near-optimal delays. >

Power density and energy dissipation of digital IC's has become one of the main concerns during the recent years. With the increased usage of battery powered devices, ubiquitous computing, and increase in implantable biomedical applications, enhancing energy efficiency of digital systems is one of the key research areas in digital IC design. For applications with a low demand on throughput, sub-threshold digital operation is one of the promising techniques for ultra-low energy operation. Moreover, global energy minimum operating point of a digital static CMOS circuit, if exists, is in the sub-threshold regime; thus, realizing global minimum energy operation. This doctoral dissertation presents different energy efficiency enhancement methods for sub-threshold digital CMOS circuits. First, a high level sub-threshold energy model is developed for rapid characterization of digital circuits. Model accuracy is validated with measurements of a circuit that was fabricated in 0.18 µm process, and with simulations for smaller feature sized technologies. Second, this model is applied to compare the energy efficiency of synchronous and asynchronous circuits. It is shown that with a suitable external completion detection mechanism, energy efficiency of asynchronous circuits in the sub-threshold regime is better than the synchronous counterparts. Process selection to minimize energy dissipation is investigated. Moreover, it is shown that with the correct choice of process options, migrating to a smaller feature sized technology increases the energy efficiency of a circuit. Architectural modifications such as parallelism, pipelining, and folding are also explored and applied to reduce energy dissipation. Finally, a current sensing completion detection system is proposed and implemented for sub-threshold asynchronous circuits. Design flows for de-synchronization of synchronous circuits are presented for various cases with detailed explanations of sub-blocks of the completion detection system. As a proof of concept example, a self-timed cardiac event detector is implemented in a 65 nm CMOS process.

Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bundled-data designs. However, two barriers to its wider adoption are: 1) missing methods to automatically implement QDI circuits and 2) enabling QDI semi-custom design. This paper proposes a new QDI design method that extends the null convention logic (NCL) asynchronous template. Also, it describes an associated semi-custom design flow for the extended template, which uses conventional electronic design automation tools to synthesize QDI circuits down to layout. The method enables using the full power of synthesis and optimization commercial tools. Illustrating this, the ISCAS85 benchmarks take 35%–43% less gates to implement, compared with conventional, pattern-based NCL design. A comparison with the Uncle tool provides indication that the proposed method is indeed a flexible and powerful approach to design asynchronous QDI circuits. Lastly, 16-b multiplier designed with the method until the layout level exhibits 170%–240% larger operations/Watt compared with an equivalent NCL design, and an almost 400% better operations/mm2 figure.

Todays, transistor level design plays major impact in the power consumption of the VLSI based design. The various logic design models are used to reduce the power consumption that includes synchronous and asynchronous design model. The operation of synchronous circuit is limited by the in phase factor of the clock pulse signal which is used to control the synchronous circuit. In contrast, asynchronous circuits are used widely because it causes low noise, require less power. It affects the less electromagnetic interference that allows reuse of the components. These asynchronous circuits are being implemented by Null Conventional Logic (NCL) which is a delay insensitive logic model. The Configuration Logic Block is the power consuming model in Field Programmable Gate Array (FPGA). This block contains the lookup table (LUT) and 27 fundamental NCL logic gates. To reduce the power consumption of this module, we use the Differential Cascade Voltage Switch Logic (DVSL). The power reduction is achieved in LUT by means of DVSL and minimizes the number transistors. This NCL, DVSL, FPGA logic element is simulated using 90 nm TSMC CMOS processing technology.

Shrinking silicon technologies, increasing logic densities and clock frequencies on FPGA lead to rapid elevation in power density, which are translated to higher on-chip temperature. Recently, the FPGA industry (e.g. Xilinx, Altera) recognized the dominance of the heat problem as one of its key design issues, which should be tackled immediately. In this paper, considering a novel temperature-aware placement and routing algorithm, a systematic methodology to achieve a more "balanced" temperature distribution in the whole FPGA device, is introduced. Since the temperature is straightforward-related with the FPGA hardware resources switching activity, the main goal of the proposed methodology is to manipulate appropriately the switching activity appeared on different regions of the FPGA. Using the temperature-aware algorithm, we redistribute the switching activity over the FPGA resources, resulting into a rather "balanced" profile. Comparing with a conventionally-placed and routed FPGA (e.g. VPR), we proved that up to 33% temperature reduction in hotspots can be achieved with negligible side effects in circuit delay, energy/power consumption and silicon area. The proposed methodology is fully-supported by the software tool called EX- VPR

In this paper, a new method of state code assignment for reduction of switching activities of state transition in asynchronous circuits is proposed. The algorithm is based a on one-hot code and modifies it to reduce switching activities. As a result, the proposed algorithm has an advantage, of 60% reduction over the conventional one-hot code assignment in terms of switching activities and code length of state assignment.

In sequential circuits, the current output can depend on both past and current inputs. However, certain kinds of sequential circuits do not refer to all of the past inputs to generate the current output; but only to a subset of past inputs. This paper investigates which subset of past inputs a sequential circuit refers to, and proposes a new classification of sequential circuits based on this criterion. While the conventional classification of sequential circuits distinguishes between synchronous and asynchronous circuits, the new classification consolidates synchronous circuits and multiple clock domain circuits into the same category. This is consistent with the notion that “multiple clock domain circuits are analogous to synchronous circuits,” and thus, the proposed classification appears valid from this perspective. It is expected that a method underlying our classification will allow a deeper understanding of sequential circuits.

Photovoltaic is a technology that converts sunlight radiation into electrical energy and has a great chance to develop in tropical countries such as Indonesia. The effect of the partially shaded condition reduces the energy generated and the efficiency of the photovoltaic farm. This paper proposes a new method for power optimization by reconfiguring the converter topologies using the Smart Clustering Method. The reconfiguration of converter topologies is based on the voltages magnitude of each string on the PV Farm clustered using the smart clustering method. Each converter has MPPT algorithm, so the total power generated by the PV farm is equal to the sum of power generated by each converter topology. The modified P&O Algorithm is used in the uniform clustering, and the firefly Algorithm is used in the non-uniform clustering. For the validation of the proposed method, this paper compared the performance of the proposed method with the performance of MPPT using single converter topologies as a conventional method.

SUMMARY This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than

Optimization for power is always one of the most important design objectives in modern nanometer IC design. Recent studies have shown the effectiveness of applying multi-bit flip-flops to save the power consumption of the clock network. However, all the previous works applied multi-bit flip-flops at earlier design stages, which could be very difficult to carry out the trade-off among power, timing, and other design objectives. This paper presents a novel power optimization method by incrementally applying more multi-bit flip-flops at the post-placement stage to gain more clock power saving while considering the placement density and timing slack constraints, and simultaneously minimizing interconnecting wirelength. Experimental results based on the industry benchmark circuits show that our approach is very effective and efficient, which can be seamlessly integrated in modern design flow.

In this paper, we propose a new asynchronous method based on a Null Convention Logic (NCL) to improve power consumption for low power integrated circuits. The reason is because the NCL based designs do not use a clock, it eliminates the problems related to the clock and its power consumption reduces significantly. To show the advantages of the selected method, we propose two design models using the synchronous circuit design method, and the NCL based asynchronous circuit design method. To test these two design models conveniently, we also propose an extra automatic test model. In this study, the AES decryption is used as an example to illustrate both methods. The two above proposed AES decryption models are simulated and synthesized at the various corners by VCS and Design Compiler tool using TSMC standard cell libraries in 65nm technology. The synthesis results of the two above mentioned models indicated that the power consumption of the NCL based asynchronous circuit model is 3 times lower than that of the synchronous circuit model, and significantly improves (from 94% to 98%) compared with the results of the other authors. The processing speed of the NCL based asynchronous circuit paradigm is able to achieve a maximum speed.