Power andPerformance Analysis for Early Design Space Exploration

Applications and architectures for embedded systems are becoming more and more complex. It is difficult to analyze complex embedded applications at early stages of the design flow without generic automated tools and methodologies. Consequently, application analysis under the real input conditions is becoming more and more important. Existing application analysis methodologies mainly focus on a single design objective. A general purpose application analysis methodology is required to satisfy multiple objectives of early design space exploration. This article proposes a general purpose application analysis methodology based on a visitor design pattern. High level source specifications are transformed into a trace tree representation by dynamic analysis. Trace tree representation is analyzed by using a visitor design pattern to get run-time characteristics of the application. Among other outcomes, application characterization and average inherited parallelism are key concerns in this article. Experimental results with MPEG-2 video decoder shows viability of the proposed methodology.

Design space exploration of microprocessor is still a challenging task for processor designers. Due to the huge design space, it is hard to determine the optimal configuration of microarchitecture parameters to satisfy the target performance and power requirements within limited time at the early stage of processor design. In this paper, a Critical Path Analysis directed Design Space Exploration (CPADSE) methodology for design space exploration of microprocessors is proposed. In CPADSE, a dependence graph model is constructed using the profile information generated during the program simulation. Then the critical paths of the dependence graph model are computed and patterns of the critical path are identified. The microarchitecture parameters mostly affecting processor`s performance or other metrics can be identified using the Plackett-Burman design method, which is always referenced as sensitivity analysis. Then the result of critical path analysis and sensitivity analysis is further used to guide the selection of search direction in both SA-CPADSE and TB-CPADSE design space search algorithms, which are proposed in this paper. Experiment result shows that for the design space exploration on SPEC 2000 benchmarks, SA-CPADSE obtains 2x speedup over baseline design space exploration algorithm SA-DSE. Additionally, TB-CPADSE on average obtains 4.3x speedup over SA-CPADSE and 7x speedup over SA-DSE. At the end of this paper, we have a detailed discussion about how to extend CPADSE methodology to design space exploration of multicore processors.

A data warehouse is a repository of data that can be analyzed to gain a better knowledge about the “goings on” in a company. The value of better knowledge can lead to superior decision making. Although this architecture has been around for a long time its use is not wide spread. Many researchers have noted the absence of its penetration in business. So, while on the one hand we find a rapid growth in the e-commerce industry and advances in hardware and software, on the other hand, very few companies seem to know how to use data warehousing technologies to succeed in e-commerce. There are companies that have successfully incorporated a data warehouse and have become pioneers and leaders in e-commerce. This article presents the success of Amazon. com in the business to consumer sector of e-commerce and the success of Wal-Mart as the leader in the business to business sector of e-commerce. Data warehousing and electronic-commerce are two of the most rapidly expanding  elds in recent information technologies. In this paper, we discuss the design of data warehouses for e- commerce environment. We discuss requirement analysis, logical design, and physical design issues in e-commerce environments. We have collected an extensive set of interesting OLAP queries for e-commerce environments, and classi ed them into categories. Based on these OLAP queries, we illustrate our design with data warehouse bus architecture, dimension table structures, a base star schema, and an aggregation star schema. We  nally present various physical design considerations for implementing the dimensional models. We believe that our collection of OLAP queries and dimensional models would be very useful in developing any real-world data warehouses in e-commerce environments. We have collected an extensive set of interesting OLAP queries for e-commerce environments, and classified them into categories. Based on these OLAP queries, we illustrate our design with data warehouse bus architecture, dimension table structures, a base star schema, and an aggregation star schema. We finally present various physical design considerations for implementing the dimensional models. We believe that our collection of OLAP queries and dimensional models would be very useful in developing any real-world data warehouses in e- commerce environments.

There are many layout design styles, the choice of which depends on the type and size of the IC. Basically we have two main classes of I Cs: standard integrated circuits (SI Cs); and application-specific integrated circuits (ASICs). TTL, CMȮS, and ECL SSI and MSI circuits containing several kinds of logic gates and macrocells (registers, counters etc., see chapter 3) belong to the class of SICs. Standard large-scale integration (LSI) and (VLSI) circuits are microprocessors and semiconductor memories (see the memory chip in Fig. 5.2). The main features of standard integrated circuits are: support of a wide range of applications; high-volume production; and low price.

The growing demand for high-performance and energy-efficient memory has accelerated the development of low-power static random-access memory (SRAM) architectures, which form a critical component of modern system-on-chip (SoC) designs. This paper presents a comprehensive analysis of a novel 11T SRAM cell, with a strong emphasis on physical design considerations. The proposed 11T cell introduces a dedicated read line and a transmission gate in place of conventional pass transistors, resulting in enhanced read/write stability and reduced power consumption. The design is implemented and evaluated using Cadence Virtuoso with TSMC 65 nm CMOS technology. Simulation results confirm that the proposed 11T cell achieves 39.56% improved write static noise margin (SNM) and 11.50% lower power dissipation and 6.7% higher write speed compared to stack transistor-based 11T architecture. Additionally, a comparative analysis involving 6T, 8T, conventional 11T, and the proposed 11T SRAM cells was performed using both TSMC 65 nm and UMC 65 nm technology nodes. The results demonstrate that TSMC 65 nm technology yields superior performance over UMC. Post-layout simulations further validate the design’s stability in the presence of parasitic effects, with all evaluations conducted at a supply voltage of 1.2 V.

This article examines electrical, thermal, and packaging considerations for realizing DC-DC converters based on neutral-point clamped (NPC) phase legs. Four variations of a three-level NPC leg are contrasted. These variants cover different device packaging technologies, viz., surface mount, and through-hole devices. The scope of variants is limited to systems with liquid cooling and converters with a cuboid shape of a limited z-axis dimension. Each variant and gate driver are designed using Altium Designer, assuming certain converter specifications. Printed circuit board (PCB) parameters are extracted using finite-element analysis (FEA) in ANSYS Q3D. Electrical switching behavior of the MOSFETs under each variant is evaluated using double-pulse testing in LTSpice. Thermal interfacing and its associated consequences on device capability utilization, manufacturing challenges, and cost are also discussed. A comparison showing the merits and limitations of all four variations based on device technology usage—the basis of comparison being volume, thermal management, cost, parasitic circuit elements, and switching behavior is presented. Furthermore, the design consideration trade-offs for building a converter are listed to achieve the application priorities. The list, along with the comparison, aids in selecting one of the four variants or their derivatives for designing converters that fall under the defined scope.

Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.

Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using HPC architectures is very sensitive to the HPC parameters. Therefore it is very important to explore the HPC design space and carefully choose the HPC parameters that result in minimum energy consumption for the application. However, since in HPC architectures, the compiler has a significant impact on the energy consumption of the memory subsystem, it is extremely important to include compiler while deciding the HPC design parameters. While there has been no previous approaches to HPC design exploration, existing cache design space exploration methodologies do not include the compiler effects during DSE. In this paper, we present a Compiler-in- the-Loop (CIL) Design Space Exploration (DSE) methodology to explore and decide the HPC design parameters. Our experimental results on HP iPAQ h4300-like memory subsystem running benchmarks from the MiBench suite demonstrate that CIL DSE can discover HPC configurations with up to 80% lesser energy consumption than the HPC configuration in the iPAQ. In contrast, tradition simulation-only exploration can discover HPC design parameters that result in only 57% memory subsystem energy reduction. Finally our hybrid CIL DSE heuristic saves 67% of the exploration time as compared to the exhaustive exploration, while providing maximum possible energy savings on our set of benchmarks.

Many demanding streaming applications share functional and structural similarities with other applications in their respective domain, e.g., video analytics, software-defined radio, and radar. This opens the opportunity for specialization to achieve the needed efficiency and/or performance.Platforms integrating many accelerators (ACCs) are a primary approach for efficient, high-performance stream computing. However, designing one platform for each application is not economical due to the high costs of nonrecurring engineering (NRE) and time-to-market (TTM). To this end, the concept of domain platforms is proposed, which takes advantage of similarities across applications and designs one unified platform to accelerate a domain of applications instead of focusing on a single reference application. This dissertation approaches designing domain platforms from a function-level (kernel-level) acceleration through a heterogeneous ACC-rich platform, where each ACC is specialized to accelerate a particular function. There is a great challenge to select ACCs allocated in the domain platform, considering the large design space and performance balance across many applications. However, current Design Space Exploration (DSE) tools only focus on an individual application in isolation (e.g., one particular vision flow) for allocating a platform, but not a set of similar applications. Multiple applications are only considered in the application bindings to an existing platform. Hence, optimizations that occur due to considering multiple applications simultaneously are missed in platform design. New DSE methodologies and tools are needed with a broader scope of application sets instead of individual applications. This dissertation introduces a novel Domain Design Space Exploration (DmDSE) methodology that broadens the DSE scope from an individual application to allocating a new heterogeneous ACC-rich platform for many applications.This dissertation defines domain characteristics to express the inherent structural and functional similarities across applications and metrics to quantitatively assess domain platforms with a balanced focus across various applications. Two novel algorithms, Dynamic Score Selection (DSS) and GenetIc Domain Exploration (GIDE), are introduced to do DmDSE and allocate domain platforms, which improve performance over application-specific platforms by 58% and 75% when only considering monolithic (single function) ACCs. A finer granularity of ACCs is beneficial for generality and performance under an area constraint. Considering multi-granularity similarities across functions, Multi-Granularity DmDSE (MG-DmDSE) extends DSE through allocating finer granular and configurable ACCs and decomposing functions in the binding. MG-DmDSE produces a more general platform that benefited 87.5% of applications, while only 50% from GIDE. With a huge design space, DmDSE suffers from a long exploration time due to a large number of complex platform evaluations. Heuristics and machine learning methods are proposed to speed up DmDSE.This dissertation introduces Greedy Guided Mutation (GGM) to speed up the mutation in the GIDE algorithm, which calculates an ACC score according to current allocation to guide mutation. Alternatively, Rapid Domain Platform Performance Prediction (RDP^3) methods are introduced to replace a large number of the slow platform assessment in domain DSE, which avoids the complex application binding exploration. In the experiments, GGM reduces 84.8% of exploration time with a 0.23% loss of the final OpenVX domain platform's performance. RDP^3, using a machine learning method, yields an even more significant speedup, saving 90.8% of exploration time with only 0.0003% performance loss. DmDSE is a milestone to broaden DSE scope from individual applications to the domain level. It tremendously pushes the domain platform design from an experience-guided, manual effort into an automated process.--Author's abstract

It is widely accepted that use of an Application Specific Instruction Set Processor (ASIP) in an embedded system can provide a solution which is much more flexible than ASICs and much more efficient than standard processors in terms of performance and power consumption. However a lack of an acceptable design methodology and supporting tools for ASIPs limits their use even today. We present in this paper a methodology for design space exploration of high performance VLIW ASIPs by modeling Application Specific Functional Units in Trimaran Compiler Infrastructure. To demonstrate the effectiveness of our strategy we consider two important applications FFT and Kalman Filter and perform compute intensive operations in these applications via special Functional Units. The results we obtain are very promising with up to 2x speed improvement.

Coarse-grained reconfigurable architectures (CGRAs) are gaining increasing attention as domain-specific accelerators due to their high flexibility and energy efficiency. These architectures offer a compelling solution for applications that require custom hardware performance while retaining a degree of programmability. However, the design space of CGRAs is inherently vast and complex, presenting significant challenges for architects to explore design choices efficiently and systematically. Existing design space exploration (DSE) methodologies for CGRAs are often time-demanding and struggle to deliver optimal solutions when confronted with high-dimensional and multi-objective design space. Therefore, we consider constructing a CGRA parameter tuning framework called MoDAF. MoDAF initializes the design space using the most representative and diverse samples. It adopts a divide-and-conquer approach, utilizing Monte Carlo Tree Search (MCTS) and space partitioning techniques to dynamically break down the complex design space into more manageable subspaces. A hybrid model handles local fluctuations within each subspace, while a dual sampling algorithm is designed to increase sampling efficiency. MoDAF also incorporates a fast evaluation model to estimate CGRA throughput and area, significantly speeding up the exploration process. Compared with previous approaches, experiments show that our proposed framework reduces the average distance from the reference set by 53.0% and the hypervolume deviation by 64.2%, while also cutting wall time by 57.5%.

In this paper a tool aimed at generating fast Fourier transform (FFT) cores targeting FPGA platforms was presented. The tool is able to generate different pipelined architectures of the FFT that provide different points of the design space: from high performance to low area implementations. The user can select the most suitable architecture based on a broad set of configuration parameters, as they are the number of points, sample size, truncation, etc. Moreover, a set of accurate estimators has been implemented to allow the designer an early and quick design space exploration before synthesizing the core. Experimental results validate our approach and provide significant measurements about the accuracy of the estimation and the tool execution time

Recent years have brought significantly increased interest in integrating wireless communication capability within factory automation systems. Such integration motivates the study of interactions among the physical layout of factory workcells, wireless communication among workcells, and improving the overall factory system performance. In this paper, we develop methods for modeling and simulating these interactions, and implement these methods into the experimental study of complex design spaces for factory automation systems. The proposed methodology for modeling, simulation, and design space exploration can be used to gain insight into approaches for improving the configuration (e.g., physical layout or wireless protocol settings) of existing factory systems, and for understanding trade-offs in the design of new systems.

Throughout the history of the chemical industry, crystals have been produced via crystallization methods that range between something as simple as allowing vats of hot concentrated solution to cool to those as complex as continuous, carefully controlled, multi-step processes which yield a crystal product of a particular size or size distribution, shape, moisture content, and purity. Crystallization is an important mass transfer operation that is often employed in the preparation of a pure product. This chapter introduces the reader to the concepts and applications of the crystallization process to water desalination and wastewater treatment through discussion of the crystallization process, crystal physical characteristics, crystallization equipment, describing equations, and design considerations. The crystallization process essentially involves three steps: formation of crystals, crystal growth, and separation of the crystals from residual liquid. The chapter provides seven illustrative examples related to the general subject of crystallization.

The Internet of Things (IoT) makes use of ubiquitous internet connectivity to form a network of everyday physical objects for purposes of automation, remote data sensing and centralized management/control. IoT objects need to be embedded with processing capabilities to fulfill these services. The design of processing units for IoT objects is constrained by various stringent requirements, such as performance, power, thermal dissipation etc. In order to meet these diverse requirements, a multitude of processor design parameters need to be tuned accordingly. In this paper, we propose a temporally efficient design space exploration methodology which determines power and performance optimized microarchitecture configurations. We also discuss the possible combinations of these microarchitecture configurations to form an effective two-tiered heterogeneous processor for IoT applications. We evaluate our design space exploration methodology using a cycle-accurate simulator (ESESC) and a standard set of PARSEC and SPLASH2 benchmarks. The results show that our methodology determines microarchitecture configurations which are within 2.23–3.69 percent of the configurations obtained from fully exhaustive exploration while only exploring 3–5 percent of the design space. Our methodology achieves on average 24.16× speedup in design space exploration as compared to fully exhaustive exploration in finding power and performance optimized microarchitecture configurations for processors.