Visitor-based application analysis methodology for early design space exploration

Early design space exploration is crucial to achieving optimal designs, when it is increasingly difficult to fit a design into a tight design space. System level exploration needs to be coupled with physical design considerations to guarantee design closure and time-to-market. This paper presents a methodology for early design space exploration aimed at power-delay trade-offs. The proposed methodology allows quick what-if analysis incorporating many design techniques. What-if analysis is performed on three ISCAS85 benchmark circuits to ascertain recipes for power or performance centric designs. Using the proposed methodology we demonstrate 32%, 17% and 32% reduction in power for 9%, 4.3% and 1.3% performance penalty respectively, the what-if analysis also shows 11.25%, 10.31% and 15.3% improvement in performance for 2.35%, 2.43% and 3.85% increase in power, respectively if the same circuits were made performance centric.

Modern embedded Systems-on-Chips (SOCs) will allow the system designer to customize Intellectual Property (IP) cores (fixed and programmable), together with custom logic and large amounts of embedded memory. As the software content in these emerging embedded SOCs begins to dominate the SOC design process, there is a critical need for support of an integrated software development environment (including compilers, simulators and debuggers). Furthermore, since many characteristics of these processor core IPs (e.g., instruction-sets, memory configurations) are increasingly customizable, the entire software toolkit chain needs to be customized and generated to support both early design space exploration (for performance, power and cost constraints), as well as high-qualify software generation. This paper first surveys recent efforts in Architecture Description Languages (ADLs) used to perform early validation and exploration of SOC architectures. The second part of the paper focuses on approaches to software toolkit generation that automatically produce the software infrastructure (e.g., compilers, simulators, debuggers) which will enable true hardware/software codesign of these emerging embedded SOCs.

Horizontally Partitioned Caches (HPCs) are a promising architectural feature to reduce the energy consumption of the memory subsystem. However, the energy reduction obtained using HPC architectures is very sensitive to the HPC parameters. Therefore it is very important to explore the HPC design space and carefully choose the HPC parameters that result in minimum energy consumption for the application. However, since in HPC architectures, the compiler has a significant impact on the energy consumption of the memory subsystem, it is extremely important to include compiler while deciding the HPC design parameters. While there has been no previous approaches to HPC design exploration, existing cache design space exploration methodologies do not include the compiler effects during DSE. In this paper, we present a Compiler-in- the-Loop (CIL) Design Space Exploration (DSE) methodology to explore and decide the HPC design parameters. Our experimental results on HP iPAQ h4300-like memory subsystem running benchmarks from the MiBench suite demonstrate that CIL DSE can discover HPC configurations with up to 80% lesser energy consumption than the HPC configuration in the iPAQ. In contrast, tradition simulation-only exploration can discover HPC design parameters that result in only 57% memory subsystem energy reduction. Finally our hybrid CIL DSE heuristic saves 67% of the exploration time as compared to the exhaustive exploration, while providing maximum possible energy savings on our set of benchmarks.

Design space exploration of microprocessor is still a challenging task for processor designers. Due to the huge design space, it is hard to determine the optimal configuration of microarchitecture parameters to satisfy the target performance and power requirements within limited time at the early stage of processor design. In this paper, a Critical Path Analysis directed Design Space Exploration (CPADSE) methodology for design space exploration of microprocessors is proposed. In CPADSE, a dependence graph model is constructed using the profile information generated during the program simulation. Then the critical paths of the dependence graph model are computed and patterns of the critical path are identified. The microarchitecture parameters mostly affecting processor`s performance or other metrics can be identified using the Plackett-Burman design method, which is always referenced as sensitivity analysis. Then the result of critical path analysis and sensitivity analysis is further used to guide the selection of search direction in both SA-CPADSE and TB-CPADSE design space search algorithms, which are proposed in this paper. Experiment result shows that for the design space exploration on SPEC 2000 benchmarks, SA-CPADSE obtains 2x speedup over baseline design space exploration algorithm SA-DSE. Additionally, TB-CPADSE on average obtains 4.3x speedup over SA-CPADSE and 7x speedup over SA-DSE. At the end of this paper, we have a detailed discussion about how to extend CPADSE methodology to design space exploration of multicore processors.

It is widely accepted that use of an Application Specific Instruction Set Processor (ASIP) in an embedded system can provide a solution which is much more flexible than ASICs and much more efficient than standard processors in terms of performance and power consumption. However a lack of an acceptable design methodology and supporting tools for ASIPs limits their use even today. We present in this paper a methodology for design space exploration of high performance VLIW ASIPs by modeling Application Specific Functional Units in Trimaran Compiler Infrastructure. To demonstrate the effectiveness of our strategy we consider two important applications FFT and Kalman Filter and perform compute intensive operations in these applications via special Functional Units. The results we obtain are very promising with up to 2x speed improvement.

In this paper a tool aimed at generating fast Fourier transform (FFT) cores targeting FPGA platforms was presented. The tool is able to generate different pipelined architectures of the FFT that provide different points of the design space: from high performance to low area implementations. The user can select the most suitable architecture based on a broad set of configuration parameters, as they are the number of points, sample size, truncation, etc. Moreover, a set of accurate estimators has been implemented to allow the designer an early and quick design space exploration before synthesizing the core. Experimental results validate our approach and provide significant measurements about the accuracy of the estimation and the tool execution time

Virtual platform prototypes are widely utilized to enable early system-level design space exploration. Accurate power models for hardware components at high levels of abstraction are needed to enable system-level power analysis and optimization. However, the limited observability of third party IPs renders traditional power modeling methods challenging and inaccurate. In this paper, we present a novel approach for extending behavioral models of black-box hardware IPs with an accurate power estimate. We leverage state-of-the-art-machine learning techniques to synthesize an abstract power model. Our model uses input and output history to track data-dependent pipeline behavior. Furthermore, we introduce a specialized ensemble learning that is composed out of individually selected cycle-by-cycle models to reduce overall complexity and further increase estimation accuracy. Results of applying our approach to various industrial-strength design examples shows that our models predict average power consumption to within 3% of a commercial gate-level power estimation tool, all while running several orders of magnitude faster.

Designing soft-errors resilient systems is a complex engineering task, which nowadays follows a cross-layer approach. It requires a careful planning for different fault-tolerance mechanisms at different system’s layers: starting from the technology up to the software domain. While these design decisions have a positive effect on the reliability of the system, they usually have a detrimental effect on its size, power consumption, performance and cost. Design space exploration for cross-layer reliability is therefore a multi-objective search problem in which reliability must be traded-off with other design dimensions.Assessing the reliability of a complex system and performing design space exploration in the early phases of the design cycle is a complex task and designers are increasing looking at stochastic models able to provide fast results to quickly drive early design decisions. This paper summarizes some of the results achieved by the authors in more than five years of research in this domain.

Many demanding streaming applications share functional and structural similarities with other applications in their respective domain, e.g., video analytics, software-defined radio, and radar. This opens the opportunity for specialization to achieve the needed efficiency and/or performance.Platforms integrating many accelerators (ACCs) are a primary approach for efficient, high-performance stream computing. However, designing one platform for each application is not economical due to the high costs of nonrecurring engineering (NRE) and time-to-market (TTM). To this end, the concept of domain platforms is proposed, which takes advantage of similarities across applications and designs one unified platform to accelerate a domain of applications instead of focusing on a single reference application. This dissertation approaches designing domain platforms from a function-level (kernel-level) acceleration through a heterogeneous ACC-rich platform, where each ACC is specialized to accelerate a particular function. There is a great challenge to select ACCs allocated in the domain platform, considering the large design space and performance balance across many applications. However, current Design Space Exploration (DSE) tools only focus on an individual application in isolation (e.g., one particular vision flow) for allocating a platform, but not a set of similar applications. Multiple applications are only considered in the application bindings to an existing platform. Hence, optimizations that occur due to considering multiple applications simultaneously are missed in platform design. New DSE methodologies and tools are needed with a broader scope of application sets instead of individual applications. This dissertation introduces a novel Domain Design Space Exploration (DmDSE) methodology that broadens the DSE scope from an individual application to allocating a new heterogeneous ACC-rich platform for many applications.This dissertation defines domain characteristics to express the inherent structural and functional similarities across applications and metrics to quantitatively assess domain platforms with a balanced focus across various applications. Two novel algorithms, Dynamic Score Selection (DSS) and GenetIc Domain Exploration (GIDE), are introduced to do DmDSE and allocate domain platforms, which improve performance over application-specific platforms by 58% and 75% when only considering monolithic (single function) ACCs. A finer granularity of ACCs is beneficial for generality and performance under an area constraint. Considering multi-granularity similarities across functions, Multi-Granularity DmDSE (MG-DmDSE) extends DSE through allocating finer granular and configurable ACCs and decomposing functions in the binding. MG-DmDSE produces a more general platform that benefited 87.5% of applications, while only 50% from GIDE. With a huge design space, DmDSE suffers from a long exploration time due to a large number of complex platform evaluations. Heuristics and machine learning methods are proposed to speed up DmDSE.This dissertation introduces Greedy Guided Mutation (GGM) to speed up the mutation in the GIDE algorithm, which calculates an ACC score according to current allocation to guide mutation. Alternatively, Rapid Domain Platform Performance Prediction (RDP^3) methods are introduced to replace a large number of the slow platform assessment in domain DSE, which avoids the complex application binding exploration. In the experiments, GGM reduces 84.8% of exploration time with a 0.23% loss of the final OpenVX domain platform's performance. RDP^3, using a machine learning method, yields an even more significant speedup, saving 90.8% of exploration time with only 0.0003% performance loss. DmDSE is a milestone to broaden DSE scope from individual applications to the domain level. It tremendously pushes the domain platform design from an experience-guided, manual effort into an automated process.--Author's abstract

All computing platforms, from mobile to supercomputers, are becoming more and more heterogeneous and massively parallel. While they can provide higher power efficiency and computation throughput, effective and confident use of these systems always requires knowledge about low-level programming. The average time necessary to develop and optimize a design on heterogeneous platforms is higher and higher compared to typical homogeneous systems. Dataflow models of computation (MoC) are quickly becoming the common practice in heterogeneous systems development. In domains such as signal processing and multimedia communication, dataflow MoCs have become accepted as standard. However, the shift from a sequential and architecture-specific MoC to a dataflow MoC still uncovers several programming and development challenges. The Cal Actor Language (CAL) is a recently-specified dataflow and actor-based language capable of concisely expressing complex and general purpose parallel applications. However, design tools supporting this language are generally not adequate to fully exploit its features and expressiveness power. In fact, they generally restrict its MoC in order to reduce the design space exploration (DSE) effort. The objective of this thesis is to provide a DSE methodology where all the features of CAL and dynamic dataflow MoCs can be exploited in a more general and effective manner. This dissertation illustrates a novel profiling, analysis and performance estimation methodology for the DSE of dynamic dataflow programs. The main research contributions of this thesis are: the formalization of a graph-based representation of the program execution called an execution trace graph (ETG); the formalization of a systematic methodology for profiling generic dynamic dataflow programs through their code interpretation; the formalization of a complete DSE methodology for dynamic dataflow programs in order to efficiently identify close-to-optimal design points according to various and tailored performance merit functions. In particular, the following design space optimization problems for dynamic dataflow programs are addressed: the analysis of the hotspots and the algorithmic bottlenecks of a parallel program; the bounding and optimization of the buffer size configuration for complex designs; the dynamic power dissipation minimization of programs implemented in multi-clock domain architecture. Furthermore, theoretical concepts like the design space critical path and the potential speedup of a dataflow application have been defined and revisited, respectively. The thesis also presents a DSE framework developed in order to demonstrate the effectiveness of this design methodology.

Optimization problems in many industrial applications are very hard to solve. Many examples of them can be found in the design of aeronautical systems. In this field, the designer is frequently faced with the problem of considering not only a single design objective, but several of them, i.e., the designer needs to solve a Multi-Objective Optimization Problem (MOP). In aeronautical systems design, aerodynamics plays a key role in aircraft design, as well as in the design of propulsion system components, such as turbine engines. Thus, aerodynamic shape optimization is a crucial task, and has been extensively studied and developed. Multi-Objective Evolutionary Algorithms (MOEAs) have gained popularity in recent years as optimization methods in this area, mainly because of their simplicity, their ease of use and their suitability to be coupled to specialized numerical simulation tools. In this chapter, we will review some of the most relevant research on the use of MOEAs to solve multi-objective and/or multi-disciplinary aerodynamic shape optimization problems. In this review, we will highlight some of the benefits and drawbacks of the use of MOEAs, as compared to traditional design optimization methods. In the second part of the chapter, we will present a case study on the application of MOEAs for the solution of a multi-objective aerodynamic shape optimization problem.

Industry trends of using ever-larger wind turbine generators and developing farms in deeper waters with longer design lives have resulted in increased importance of optimisation of monopile foundation structures due to their favourability over more complex foundation types. Optimisation is crucial to adequately assess feasibility of monopiles, and to efficiently design the structures to minimise capital expenditure and levelised cost of energy. This paper presents a methodology for site-wide design space exploration and optimisation of monopiles to address these challenges, using OPTIF, Arup’s in-house tool for design and optimisation of offshore wind foundation structures. The methodology employs heuristic and numerical optimisation approaches to rapidly optimise many thousands of monopile geometries for given site conditions and design constraints under the governing load cases, providing both designs that minimise total mass, and valuable insights into site-specific effects. The methodology is applicable at both early-stage and later FEED/detailed design stages, employing highly-accurate, site-specific loads analysis fully integrated with the structural optimisation to enable accurate early stage foundation weight estimates, provide valuable insight to inform advanced clustering, and allow for position-specific optimised geometries at later stages. The methodology is applied to an early-stage design case study to identify optimum mudline diameters across a typical site, and this study is used to illustrate the possibility for more advanced clustering methods informed by rapid site-wide mass sensitivity studies using varied input parameters and clustering approaches.

Recent years have brought significantly increased interest in integrating wireless communication capability within factory automation systems. Such integration motivates the study of interactions among the physical layout of factory workcells, wireless communication among workcells, and improving the overall factory system performance. In this paper, we develop methods for modeling and simulating these interactions, and implement these methods into the experimental study of complex design spaces for factory automation systems. The proposed methodology for modeling, simulation, and design space exploration can be used to gain insight into approaches for improving the configuration (e.g., physical layout or wireless protocol settings) of existing factory systems, and for understanding trade-offs in the design of new systems.

As computation becomes increasingly limited by data movement and energy consumption, exploiting locality throughout the memory hierarchy becomes critical to continued performance scaling. Moving computation closer to memory presents an opportunity to reduce both energy and data movement overheads. We explore the use of 3D die stacking to move memory-intensive computations closer to memory. This approach to processing in memory addresses some drawbacks of prior research on in-memory computing and is commercially viable in the foreseeable future.Because 3D stacking provides increased bandwidth, we study throughput-oriented computing using programmable GPU compute units across a broad range of benchmarks, including graph and HPC applications. We also introduce a methodology for rapid design space exploration by analytically predicting performance and energy of in-memory processors based on metrics obtained from execution on today's GPU hardware. Our results show that, on average, viable PIM configurations show moderate performance losses (27%) in return for significant energy efficiency improvements (76\% reduction in EDP) relative to a representative mainstream GPU at 22nm technology. At 16nm technology, on average, viable PIM configurations are performance competitive with a representative mainstream GPU (7% speedup) and provide even greater energy efficiency improvements (85\% reduction in EDP).

Alchemy : A Methodology for Scalable RTL Design Space Exploration