Power distribution network design optimization with on-die voltage-dependent leakage path

Several solutions to decrease the propagation of simultaneous switching noise (SSN) in power distribution network (PDN) were evaluated for boards with active components. Radiated emission of the boards using power track, 2 cell symmetric power island (or one-cell Electromagnetic Band Gap (EBG) with square patches or asymmetric EBG was measured using a Reverberation Chamber, and the results were compared to a standard power plane design. The effect of the various EBG structures on the noise in PDN, and the radiated emission due to printed circuit boards was investigated.

The selection of decoupling capacitors (decap) is a critical but tedious process in power distribution network (PDN) design. In this paper, an improved decap-selection algorithm based on deep reinforcement learning (DRL), which seeks the minimum number of decaps through a self-exploration training to satisfy a given target impedance, is presented. Compared with the previous relevant work: the calculation speed of PDN impedance is significantly increased by adopting an impedance matrix reduction method; also, the enhanced algorithm performs a better convergence by utilizing the techniques of double Q-learning and prioritized experience replay; furthermore, a well-designed reward is proposed to facilitate long-term convergence when more decaps are required. The proposed algorithm demonstrates the feasibility of achieving decent performance using DRL with pre-trained knowledge for more complicated engineering tasks in the future.

In this paper, the reduction of power distribution network noise and jitter at high-speed output buffer by using on-chip linear voltage regulator module circuit is introduced and analyzed. The transient response of typical on-chip linear VRM circuit is analyzed in power gating condition. When the on-chip linear VRM circuit is inserted between on-chip PDN and operating high-speed output buffers, the on-chip PDN noise and jitter at output buffer are significantly reduced. The larger on-chip decoupling capacitor leads to the lower PDN noise generated by on-chip linear VRM circuit. The on-chip linear VRM also reduces the impact of the aggressor buffer to the victim buffer in different PDN, resulting in the improved performance of the victim buffer. Reduction of PDN noise and jitter at output buffer using on-chip linear VRM are validated based on SPICE simulation with 110 nm CMOS technology library.

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a greater challenge to the design of a power distribution network (PDN). Power rails merging is a popular option adopted today in a PDN design as the provision of numerous power rails is no longer feasible due to form factor limitation and cost constraint. In this paper, a study of power integrity challenges in a high-speed input/output design using power rails merging scheme is presented. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

The problem of optimum design of tree-shaped power distribution networks with respect to the voltage drop effect is addressed in this paper. An approach for the width adjustment of the power lines supplying the circuit's major functional blocks is formulated, so that the network occupies the minimum possible area under specific voltage drop constraints at all blocks. The optimization approach is based on precise maximum current estimates derived by statistical means from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit.

Modern electronic devices such as tablets and smartphones are getting more powerful and efficient. The demand in feature sets, functionality and usability increase exponentially and this has posed a great challenge to the design of a power distribution network (PDN). Power rails merging is a popular option used today in a PDN design as numerous power rails are no longer feasible due to form factor limitation and cost constraint. In this paper, the criteria and limitations for power rails merging are discussed. Despite having all the advantages such as pin count reduction, decoupling capacitors sharing, lower impedance and cost saving, power rails merging can however, introduce coupling noise to the system. In view of this, a PDN design with power rails merging that fulfills design recommendations and specifications such as noise target, power well placement, voltage supply values as well as power supply quadrant assignment is extremely important.

Algorithms featuring fast and accurate estimation of worst-case eye diagram have been proposed to replace the time-consuming random bit simulation in channel design. However, when the interaction between nonlinear I/O circuits and power distribution network (PDN) noise is included, most of those approaches fail to maintain accuracy. Based on the superposition of multiple bit pattern responses (SMBP) concept, Ren and Oh [1] developed an algorithm to fast predict the eye diagram that theoretically captures any nonlinearity in the circuit. In this paper, a test circuit with PDN was constructed to examine the performance of this algorithm. The experiment results show good agreement with the results simulated by long PRBS in HSPICE.

An important application of 3-D integration technology is stacked processor-DRAM systems. One of the major design issues in 3-D processor-DRAM stacks is power delivery. Presence of hot spots, high density power regions, in processor die poses serious challenges to the design of power distribution network (PDN). In this paper, we investigate solutions to ensure power integrity in the hot spot regions.

With increasing design complexity, as well as continued scaling of supplies, the design and analysis of power distribution networks poses a difficult problem in modern IC design. We propose several closed-form solutions for power distribution network optimization and analysis which explicitly take into consideration the mesh topology. An RLC model for on-chip power distribution networks is presented for array and wire bonded integrated circuits including inter block decoupling capacitors and impedances. One of the more common design techniques for power distribution networks PDN is the determination of the impedance & supply noise. Current-mode technique is used. By using this current mode technique noise and impedance, voltage is analyzed.

The rapid advancement of artificial intelligence (AI) has accelerated the semiconductor industry, driving chip performance requirements to unprecedented levels. However, conventional system-on-chip (SoC) designs are increasingly constrained by the physical and economic limits of monolithic scaling, where continued transistor miniaturization yields diminishing returns and rising fabrication costs. To address these challenges, the industry has shifted toward chiplet-based heterogeneous integration and advanced packaging technologies. By interconnecting multiple specialized chiplets through high-density, high-bandwidth interfaces, this modular approach improves scalability, reusability, and cost efficiency while enabling faster time-to-market. However, chiplet-based systems introduce significant design complexity, particularly in signal integrity (SI) and power integrity (PI), where highly constrained interconnects and power delivery networks must meet stringent electrical requirements. Traditional design methodologies rely heavily on expert-driven manual tuning and extensive full-wave electromagnetic simulations using electronic design automation (EDA) tools, resulting in long design cycles that can span weeks or months. To overcome these limitations, this thesis investigates the application of AI, particularly deep reinforcement learning (RL), to automate and optimize chiplet-based system design with a focus on SI and PI challenges in advanced packaging technologies. The research initially explores a supervised learning approach using convolutional neural networks (CNNs) to classify signal impairments from eye diagrams. While effective, this approach reveals a critical dependence on large labeled datasets, which are scarce in SI/PI domains, motivating a shift toward RL for autonomous design space exploration without labeled data. The first major contribution proposes an RL framework for automated power distribution network (PDN) design in a four-chiplet system. Two RL algorithms, Dueling Double Deep Q-Network (DDDQN) and Proximal Policy Optimization (PPO), are evaluated under different reward strategies. Results show that dense analytical rewards based on power domain squareness and bump proximity enable the RL agent to achieve lower self-impedance than human-designed PDNs, ensuring power integrity across 28 power domains. The complete PDN layout, which typically requires three months of manual effort, is generated in under one hour using a single GPU. The second contribution focuses on signal integrity optimization for chiplet interconnects in CoWoS redistribution layers (RDLs). An RL agent is trained using a reward function that balances eye width, voltage transfer function (VTF) crosstalk, and interconnect density. The agent explores design variations across data rates from 4 to 32 GT/s using a simulation environment integrated with commercial EDA tools. Experimental results demonstrate up to 24.67% improvement in eye width and over 22 dB reduction in VTF crosstalk while satisfying UCIe electrical specifications. The training process also generates labeled datasets for future supervised learning. The third contribution introduces an RL-based routing framework for UCIe bridge interconnects in advanced System-in-Package (SiP). Using Proximal Policy Optimization, the framework learns to generate routing layouts that comply with constraints such as ground-signal-ground structures, layer assignment, and congestion avoidance. It supports all UCIe module configurations and produces design rule check-compliant solutions within 100 training episodes, reducing design time from four weeks to less than one hour while improving signal distribution and reducing via usage. In summary, this thesis presents a unified AI-driven methodology for addressing SI and PI challenges in chiplet-based systems. The proposed RL frameworks significantly outperform traditional design approaches in both efficiency and quality, demonstrating the potential of deep RL to enable scalable and intelligent design automation for advanced packaging and chiplet-based architectures.

This paper presents cross entropy (CE) optimization for optimal design of water distribution networks (WDN) under demand uncertainty. In design of WDNs, it is desired to achieve a minimum cost WDN that provides higher reliability in meeting the demands. To achieve these goals, an optimization model is formulated for design of WDNs with an objective of minimizing the total cost of WDN subject to meeting the nodal demands at a specified system reliability, mass conservation and other physical constraints. The uncertainty in future water demands is modeled using the theory of fuzzy random variable (FRV). The water demand at each node is assumed to be following a normal distribution with a fuzzy mean, and 10 % (or 20 %) of the fuzzy mean as its standard deviation. The water demand is represented as a triangular fuzzy number with the random demand as its kernel, and the interval of ±5 % (or ±10 %) variation of the random demand as its support for two scenarios. The fuzzy random system reliability (R) of WDNs is defined on the basis of necessity measure to assess system performance under fuzzy random demands and crisp head requirements. The latin hypercube sampling method is adopted for sampling of uncertain demands. The methodology is applied to two WDNs, and optimization models are solved through cross entropy optimization for different levels of reliability, and generated tradeoffs between the cost and R. On comparing the solutions obtained with the proposed methodology with earlier reported solutions, it is noted that the proposed method is very effective in producing robust optimal solutions. On analyzing the tradeoffs between reliability and costs, the results show that negligence of uncertainty can lead to under design of the WDNs, and the cost increases steeply at higher levels of reliability. The results of the two case studies demonstrate that the presented CE based methodology is effective for fuzzy-probabilistic design of WDNs.

Tradeoffs among inductance, area, and resistance of power distribution grids are evaluated in this chapter. As discussed in Sect. 1.3, design objectives, such as low impedance (low inductance and resistance), small area, and low current densities (for improved reliability ), are typically in conflict. It is therefore important to make a balanced compromise among these design goals based upon application-specific constraints. A quantitative model of the inductance/area/resistance tradeoff in high performance power distribution networks is therefore necessary to achieve an efficient power distribution network. Another important goal is to provide quantitative guidelines to these tradeoffs and to bring intuition to the design of high performance power distribution networks.

Distribution network design is one of the most essential strategic decisions in logistics systems and supply chains, as it structures the network by determining the number of echelons and specifying the types, quantities, and locations of various facilities. This chapter presents decision-support models for distribution and logistics network design, covering both continuous location models (gravity location models) and discrete network design models (capacitated/uncapacitated and their relevant variants). Comprehensive numerical experiments based on the same case study offer a direct comparison of these different network design approaches. Furthermore, as one of the most disruptive technologies in Industry 5.0, the impact of generative AI (GenAI) and large language models (LLMs) on the research and education of distribution network design is thoroughly analyzed. Our experiments demonstrate that GenAI and LLMs are powerful tools in providing structured introductions to existing problems, guiding model selection and explanation, assisting with coding and code clarification, facilitating model comparison, and generating initial ideas for new research questions in distribution and logistics network design. However, they also face reliability and accuracy challenges, exhibit limited critical thinking capabilities, and struggle to address emerging research questions. Our findings offer valuable guidance for incorporating GenAI tools and LLMs into research and educational processes in distribution and logistics network design.

In recent years, interconnect issues emerged as major performance challenges for Two-Dimensional-Integrated-Circuits (2D-ICs). In this context, Three-Dimensional-ICs (3D-ICs), which consist of several active layers stacked above each other, offer a very attractive alternative to conventional 2D-ICs. However, 3D-ICs also face many challenges associated with the Power Distribution Network (PDN) design due to the increasing power density and larger supply current compared to 2D-ICs. As an important part of 3D-IC PDNs, Power/Ground (P/G) Through-Silicon-Vias (TSVs) should be well-managed. Excessive or ill-placed P/G TSVs impact the power integrity (e.g. IR-drop), and also consume a considerable amount of chip real estate. In this work, we propose a Mixed-Integer-Linear-Programming (MILP)-based technique to plan the P/G TSVs. The goal of our approach is to minimize the average IR-drop while satisfying the total area constraint of TSVs by optimizing the P/G TSV placement. Therefore, the locations, sizes and the total number of the P/G TSVs are co-optimized simultaneously. The experimental results show that the average IR-drop can be reduced by 11.8 % in average using the proposed method compared to a random placement technique with a much smaller runtime.

Power has becomes one of the crucial parameter while designing a SOC ICs. Power analysis of a circuit is important for reliability check, better design of power distribution network, packaging decisions and to solve power issues during test. High switching at a time demands high instantaneous current from power supply network. Which gates experience V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> drop leading to increase in delay of the circuit. Power consumed by circuit is proportional to switching activity at gate outputs and capacitance associated with it. Most of the previous work consider switching activity over entire clock period, however this is very pessimistic approach. All gates do not switch at the same time because of associated delays, thus peak switching occurring at an instant of time should be considered. In this paper we formulate an Integer Linear Programming for computing maximum transitions in the circuit at any instant time as well as during entire clock period. This method identifies a vector pair which provides the highest activity in the circuit. The proposed method captures the impact of glitches occurring during signal propagation. Our analysis shows that the maximum 75% of total gates can switch at any time instant and the maximum 625% of total gates can switch during clock period.