Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.

Multicycle (multipattern) scan-based tests contain multiple clock cycles between scan operations. Each such clock cycle defines a pattern of the test. Multipattern tests require fewer clock cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of clock cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

<p>Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.</p> <p>At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.</p> <p>We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.</p> <p>In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced</p> <p>by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.</p>

Background: The Operational amplifier (op-amp) is the building block of linear integrated electronics, therefore proposing newer design models with improved parameters is an essential landmark in the electronics industry in the hunt for a faster and more efficient design. Objective: To attain high speed and low power supply, the authors designed an op-amp using three different techniques. Initially compensating network was designed and simulated but the resultant output voltage saturates in inverting and non-inverting modes. Methods: Voltage feedback op-amp (VFOA) and current feedback op-amp (CFOA) were proposed to achieve the target. The authors have successfully designed the circuit, but the power dissipated is less and Common Mode Rejection Ratio (CMRR) is high in CFOA in comparison to VFOA. Results: The results are simulated for three different configurations and inverting configuration results in remarkable results in comparison to a non-inverting and differential amplifier. Inverting configuration using VFOA results in 91.22dB, and 0.0131W CMRR and power dissipation, respectively, while that of CFOA results in 97.34dB, and 0.0129W CMRR, and power dissipation, respectively. Conclusion: 1.6% improvement in CMRR and a 26.8% improvement in power dissipated for the proposed CMOS CFOA in comparison to the proposed VFOA. All the validations are done by plotting the bode plot and Nyquist plot.

A double Hamming distance‐based 2D reordering method is proposed for a test set with don't care bits ( X s) to reduce scan‐in power and compress test patterns. In this method, the rows and columns in the test set are reordered sequentially so that similar rows or columns are aggregated together. Being different from other reordering‐based methods, the authors' method reorders every two rows or columns with more identical bits closer in the whole reordering process, where more X s are clustered. Each X is then replaced with 0 or 1 using minimum transition filling scheme to minimise '1‐0' and '0‐1' logical state transitions. A small number of the logic state transitions cause low switching activity, which not only reduces scan‐in power consumption but also facilitates code‐based test pattern compression. Experimental results show that their proposed method achieves peak and average power reductions of 18.01 and 12.97% compared to the state‐of‐the‐art method, respectively. Furthermore, the compression ratio of alternating shifted frequency directed run‐length coding is improved to 73.76% in average utilising their proposed method.

Functional broadside tests address overtesting due to high-power dissipation by creating functional operation conditions during the clock cycles where delay faults are detected. Guided by their switching activity, it is possible to generate a low-power test set whose switching activity does not exceed the switching activity possible during functional operation. This brief applies the same approach to the generation of a low-power diagnostic test set. Excessively high switching activity can cause unexpected fault effects to appear, which will reduce the accuracy of fault diagnosis. This is avoided with a low-power diagnostic test set. Functional broadside tests are also used for avoiding diagnostic tests with unnecessarily low switching activity. The procedure described in this brief is the first to generate low-power diagnostic tests under functional constraints on switching activity as given by functional broadside tests.

This paper presents an operational-transconductance-amplifier (OTA) for ultra-low power applications with high CMRR (common mode rejection ratio) and PSRR (power supply rejection ratio). The proposed OTA is a three-stage design. In order to attain the lower supply voltage and high CMRR, a bulk-driven differential pair with the tail current source has been considered as the first stage. The current mirror biasing technique makes sure that all the transistors operate in subthreshold region. A common source amplifier has been opted with current mirror as a load in second stage. At last, common source inverting amplifier is third stage of the designed OTA. The circuit has been designed and synthesized using cadence virtuoso simulator in 180 nm CMOS technology. It has been found that these stages are helpful in achieving high low-frequency gain. Hence, CMRR and PSRR also increase in significant amount. The results describe that the proposed design offers low-frequency gain of 58 dB with CMRR of 72 dB and PSRR of 56 dB for a supply voltage (\( V_{DD} \)) of 0.5 V. The proposed OTA provides the power dissipation of 1.8 µW at \( V_{DD} \) = 0.5 V. Also, the low-frequency gain of 57 dB, CMRR of 70 dB and PSRR of 55 dB with a power dissipation of 2.5 µW have been measured at \( V_{DD} \) = 0.6 V.

In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates such that the switching activities at the output of the connected to gates are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement, i.e., the original circuit and the transformed circuit cannot be distinguished by observing the input and output behavior as long as the transformed circuit is clocked a finite number of cycles before applying any useful inputs. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of each individual transformation is polynomial in the size of the circuit, allowing the processing of large designs.

Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weight-based scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC’99 and OpenRISC benchmark circuits.

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

It is a highly tough undertaking to build an analogue circuit, especially one that consumes little power [1-5]. A basic component in many analogue integrated circuits like ADC, Gm-C filter and Delta Sigma modulator is the Operational Transcondactance Amplifier commonly known as the OTA. In all of these integrated circuits, the structure of the OTA is of fundamental importance. Gain Bandwidth (GBW), DC Gain, Common Mode Rejection Ratio (CMRR) and average power are performance characteristics that decide the selection of the OTA [6]. A well-designed OTA that has outstanding processing attributes such as speed, power consumption, gain and GBW is an accomplishment in itself [15]. This chapter mainly examines the performance parameters theoretically as well as analytically, which determines the design of OTA. Optimization strategies which are applicable to low voltage and low power applications, notably at the level of the transistor are also examined.

Adding vision capabilities to wireless sensors nodes (WSN) for the Internet-of-Things requires imagers working at ultra-low power (ULP) in nanometer CMOS systems-on-chip (SoCs). Such performance can be obtained with time-based digital pixel sensors (DPS) working at ultra-low voltage (ULV), at the expense of lower dynamic range, higher fixed-pattern noise (FPN) and thus poorer image quality. To address this problem, three key techniques were developed in this work for DPS pixels: wide-range adaptive body biasing, low- $R_{{\rm on}}$ gating of the 2-transistor in-pixel comparator and digital readout performing delta-reset sampling with low switching activity and robust timing closure. These concepts were demonstrated by designing and fabricating a 128 $\times$ 128 CMOS image sensor array in a 65 nm low-power CMOS logic process. Operating at 0.5 V, it features an FPN of 0.66%, a dynamic range of 42 dB and a fill factor of 57% with a 4 µm pixel pitch, while consuming only 17 pJ/(frame.pixel) and 8.8 µW at 32 fps. These performances combined with the small silicon area of 0.69 mm 2 makes the imager perfectly suitable for integration in ULP SoCs, targeting WSN applications.

A new phase detector is proposed and analyzed. Its linear differential structure leads to significant advantages such as the absence of a dead zone, an insensitivity to common mode noise on input signals, a low switching activity that reduces noise and power dissipation, and finally, a good acquisition behaviour. The proposed detector can detect phase differences between various signals selected from a broad class of clock signal waveform types. Moreover it has a very low phase offset, in spite of process variations. Results presented in this paper show that the proposed detector can cover a wide range of frequencies that reaches up to 2 GHz when implemented with TSMC 0.35 micron CMOS. The detector remains accurate up to the highest experimental frequencies. Its simple topology uses only 26 MOS transistors, most of which can be of minimum size.

This paper discusses a low-power test scheme compatible with both test compression and built-in self-test environments. The key contribution is a detailed analysis showing that a simple power-aware controller may allow significant reductions of toggling rates when feeding scan chains with either decompressed test patterns or pseudorandom vectors. While the proposed solution requires minimal modifications of existing DFT logic, its use results in a low switching activity during all phases of scan test: loading, capture, and unloading. It reduces power consumption to or below a level of a functional mode, thus helping to resolve problems related to power dissipation, voltage drop, and increased temperature.