Data driven power optimization of sequential circuits

Retiming is an effective technique to optimize the performance of synchronous sequential circuits. This paper proposes a method to improve the effectiveness of retiming by transforming the sequential circuit. Bottlenecks which prevent retiming to achieve a desired clock period are identified. Conditions to eliminate the retiming bottlenecks are derived. These conditions are satisfied by a process of identifying sub-circuits and satisfying a set of timing constraints on the sub-circuits. The transformed circuit, which satisfies the timing constraints, can be retimed to achieve the desired clock period. If the original circuit has its initial state specified, our method always generates the final circuit with an equivalentinitial state. Experimental results on a variety of sequential benchmark circuits demonstrate significant performance improvement.

Multicycle (multipattern) scan-based tests contain multiple clock cycles between scan operations. Each such clock cycle defines a pattern of the test. Multipattern tests require fewer clock cycles for test application compared with single-pattern or two-pattern tests for the same target faults. In addition, this paper demonstrates that patterns appearing later in a test typically have lower switching activity than patterns appearing earlier in the test. Based on these observations, the paper presents a static test compaction procedure for multipattern tests that targets a reduction in switching activity while reducing the number of clock cycles required for test application. The procedure is based on an operation called test merging. Merging of a test pair causes the patterns from both tests to appear in a single test. By placing the patterns from a test with a high switching activity at the end of a merged test, their switching activity can be reduced. The proposed procedure combines the test merging procedure with a procedure that modifies a test set so as to reduce its switching activity. Through this procedure it takes advantage of the opportunities created by test merging to reduce the switching activity of patterns that appear later in a test.

A novel explicit-pulsed dual-edge triggered sense-amplifier flip-flop (DET-SAFF) for low-power and high-performance applications is presented in this paper. By incorporating the dual-edge triggering mechanism in the new fast latch and employing conditional precharging, the DET-SAFF is able to achieve low-power consumption that has small delay. To further reduce the power consumption at low switching activities, a clock-gated sense-amplifier (CG-SAFF) is engaged. Extensive post-layout simulations proved that the proposed DET-SAFF exhibits both the low-power and high-speed properties, with delay and power reduction of up to 43.3% and 33.5% of those of the prior art, respectively. When the switching activity is less than 0.5, the proposed CG-SAFF demonstrates its superiority in terms of power reduction. During zero input switching activity, CG-SAFF can realize up to 86% in power saving. Lastly, a modification to the proposed circuit has led to an improved common-mode rejection ratio (CMRR) DET-SAFF.

Functional broadside tests address overtesting due to high-power dissipation by creating functional operation conditions during the clock cycles where delay faults are detected. Guided by their switching activity, it is possible to generate a low-power test set whose switching activity does not exceed the switching activity possible during functional operation. This brief applies the same approach to the generation of a low-power diagnostic test set. Excessively high switching activity can cause unexpected fault effects to appear, which will reduce the accuracy of fault diagnosis. This is avoided with a low-power diagnostic test set. Functional broadside tests are also used for avoiding diagnostic tests with unnecessarily low switching activity. The procedure described in this brief is the first to generate low-power diagnostic tests under functional constraints on switching activity as given by functional broadside tests.

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >

Optical interconnects and carbon nanotubes (CNTs) present promising options for replacing the existing Cu-based global/semiglobal (optics and CNT) and local (CNT) wires. We quantify the performance of these novel interconnects and compare it with Cu/low-kappa wires for future high-performance integrated circuits. We find that for a local wire, a CNT bundle exhibits a smaller latency than Cu for a given geometry. In addition, by leveraging the superior electromigration properties of CNT and optimizing its geometry, the latency advantage can be further amplified. For semiglobal and global wires, we compare both optical and CNT options with Cu in terms of latency, energy efficiency/power dissipation, and bandwidth density. The above trends are studied with technology node. In addition, for a future technology node, we compare the relationship between bandwidth density, power density, and latency, thus alluding to the latency and power penalty to achieve a given bandwidth density. Optical wires have the lowest latency and the highest possible bandwidth density using wavelength division multiplexing, whereas a CNT bundle has a lower latency than Cu. The power density comparison is highly switching activity (SA) dependent, with high SA favoring optics. At low SA, optics is only power efficient compared to CNT for a bandwidth density beyond a critical value. Finally, we also quantify the impact of improvement in optical and CNT technology on the above comparisons. A small monolithically integrated detector and modulator capacitance for optical interconnects (~10 fF) yields a superior power density and latency even at relatively lower SA (~20%) but at high bandwidth density. At lower bandwidth density and SA lower than 20%, an improvement in mean free path and packing density of CNT can render it most energy efficient.

The authors show new guidelines for V/sub dd/ and threshold voltage (V/sub th/) scaling for both the logic blocks and the high-density SRAM cells from low power-dissipation viewpoint. For the logic operation, they have estimated the power and the speed for inverter gates with a fanout=3. They find that the optimum V/sub dd/ is very sensitive to switching activity in addition to the operation frequency. They propose to integrate two sets of transistors having different V/sub dd/s on a chip. In portions of the chip with high frequency or high switching activity, the use of H transistors in which V/sub dd/ and V/sub th/ are moderately scaled is helpful. On the other hand, in low switching activity blocks or relatively low frequency portions, the use of L transistors in which V/sub dd/ should be kept around 1-1.2 V is advantageous. A combination of H and L is beneficial to suppress power consumption in the future. They have investigated the yield of SRAM arrays to study the optimum V/sub dd/ for SRAM operation. In high-density SRAM, low V/sub th/ causes yield loss and an area penalty because of low static noise margin and high bit leakage especially at high temperature operation. V/sub th/ should be kept around 0.3-0.4 V from an area size viewpoint. The minimum V/sub dd/ for SRAM operation is found to be 0.7 V in this study. It is also found that the supply voltage for SRAM cannot be scaled continuously.

At-speed scan testing, based on ATPG and ATE, is indispensable to guarantee timing-related test quality in the DSM era. However, at-speed scan testing may incur yield loss due to excessive IR-drop caused by high test (shift & capture) switching activity. This paper discusses the mechanism of circuit malfunction due to IR-drop, and summarizes general approaches to reducing switching activity, by which highlights the problem of current solutions, i.e. only reducing switching activity for one capture while the widely used at-speed scan testing based on the launch-off-capture scheme uses two captures. This paper then proposes a novel X-filling method, called double-capture (DC) X-filling, for generating test vectors with low and balanced capture switching activity for two captures. Applicable to dynamic & static compaction in any ATPG system, DC X-filling can reduce IR-drop, and thus yield loss, without any circuit/clock modification, timing/circuit overhead, fault coverage loss, and additional design effort.

Scan-based logic built-in self-test (LBIST) is widely used for supporting the in-system test in automotive systems. Although this technology has the advantage of low-cost testing, it suffers from low fault coverage and high switching activity during the test. This can lead to many undetected defects, excessive heat dissipation, and IR drop, inducing catastrophic risks to functional safety. Therefore, improving these two key factors is crucial to alleviate reliability problems in the automotive domain. Most previous works have focused on controlling the enormous toggling level of random patterns; however, one of the main disadvantages of these approaches is low fault coverage. Unfortunately, additional hardware costs associated with memory elements or test points are required for detecting the remaining faults. We propose a novel LBIST scheme based on weight-aware scan grouping and scheduling (WGS) to overcome these difficulties. Since the required test time of each automotive product is limited, the proposed scheme freezes the test time and focuses on improving both aforementioned factors significantly. Our approach divides scan cells into two categories: the coverage-efficient scan group and power-efficient scan group, and then it conducts weight-based scan cell reordering. Biased random patterns are fed to enhance fault coverage for the first category. For the second category, scheduling and disabling are performed to reduce switching activity. Finally, physical-aware reordering based on an inverter is performed to reduce routing overhead. Experimental results demonstrate the feasibility of the WGS methodology on the ITC’99 and OpenRISC benchmark circuits.

State assignment is the most critical step in the synthesis and optimization of sequential circuits as it significantly impacts sequential circuits area and power. Due to the high complexity of the state assignment problem and the ineffectiveness of existing deterministic algorithms in generating good solutions, evolutionary algorithms can be employed to obtain more effective state assignment solutions. In this paper, we propose a probabilistic tabu search (PTS) state assignment algorithm that is employed for the optimization of area and power of sequential circuits. The proposed algorithm is based on tabu search with the addition of exploiting code swap probabilities to prune the search space more effectively. Code swap probabilities are updated dynamically during the execution of the algorithm in such a way that code swaps that result in relatively inferior solutions will be assigned lower probabilities while those that result in good solutions will be assigned higher probabilities. In addition, tabu list size is changed dynamically during execution to help the algorithm get out of local minima. Based on experimental results, we show that the proposed PTS state assignment algorithm is more effective than all existing state assignment algorithms as it generates state assignment solutions with significantly lower area and power.

We describe a method of polynomial simulation to calculate switching activities in a general-delay logic circuit. This method is a generalization of the exact signal probability evaluation method due to Parker and McCluskey, which has been extended to handle temporal correlation and arbitrary transport delays. The method can target both combinational and sequential circuits. Our method is parameterized by a single parameter l, which determines the speed-accuracy tradeoff. l indicates the depth in terms of logic levels over which spatial signal correlation is taken into account. This is done by only taking into account reconvergent paths whose length is at most l. The rationale is that ignoring spatial correlation for signals that reconverge after many levels of logic introduces negligible error. When l = L, where L is the total number of levels of logic in the circuit, the method will produce the exact switching activity under a zero delay model, taking into account all internal correlation. We present results that show that the error in the switching activity and power estimates is very small even for small values of l. In fact, for most of the examples, power estimates with l = 0 are within 5% of the exact. However, this error can be higher than 20% for some examples. More robust estimates are obtained with l = 2, providing a good compromise between speed and accuracy.

This paper presents a field-programmable gate array (FPGA)-based emulator for rapidly prototyping a non-volatile (NV)-FPGA-based system on chip (SoC) where an FPGA, a central processing unit, and other peripheral modules are integrated into a single chip to address the difficulty in estimating the usefulness of an NV-FPGA-based SoC on a target system. By mimicking the NV-memory device as a sequential logic circuit, a virtual NV-FPGA SoC is implemented on a commercial FPGA board, and its system-level functional verification is performed. As a typical design example, the proposed hardware is implemented on a Digilent Basys 3 board. A fundamental arithmetic logic circuit is implemented on the NV-FPGA, and its logical behavior is the same as that of the original circuit, and NV-logic-specific functions, i.e. store and recall operations are successfully confirmed. Additionally, a 96.3% power reduction is estimated by the NV-FPGA SoC compared to that of a volatile FPGA SoC system under 1.83% of activity ratio.

Logic circuits in digital electronics can generally be classified two categories-combinational and sequential logic circuits.There are several software-based applications and hardware description languages to describe the structure and behavior of electronic circuits.Although it is an easy to construct a state transition table from the state transition diagram,creating an excitation table according to the memory element type in the sequential circuit design is a very laborious and time-consuming task.After the logic functions extracted from the state transition tables are obtained,logic design verification can be carried out by a conventional simulator.This will require time and persistence much like learning any other skill.Computer science degrees include courses focused mainly on programming languages.There’s a strong case to be made for use of skills acquired in programming courses to shorten the learning curve.Thus, this work has proposed a method for the implementation of the circuit only the state equations of the sequential circuit without dealing with excitation tables.This eliminates the process of constructing the circuit schematically, since it does not require flip-flop selection.In this method, since the state equations can be expressed through buttonbox,checkbox,textbox etc.which are the basic elements of the programming language,the behavior of the circuit can be observed in a very short time.

Exploiting data encoding and reordering for low-power streaming in systolic arrays

This paper presents a new algorithm on lower-power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. It results in increasing the area of spurious switching activity region, and further reducing the switching activity with gated-clocks during trace-back operation. With the SYNOPSYS power estimation tool, DesignPower, our experimental result shows on the average 40% reduction in power with the same latency at a cost of 23% increase in area against the trace-back unit introduced by Truong et al. (1992). The proposed survivor memory scheme can be applied to the digital communication systems for targeting low power consumption.