Performance optimization of sequential circuits by eliminating retiming bottlenecks

~ NJ 07974 Abstract - This paper addresses the problem of simukating transition faults in synchronous sequential circuits. After presenting the concept of the transition fault modell for sequential circuits, we present a fault simulation algorithm for transition faults. The algorithm is a modification of PROOFS, a parallel, differential fault simulation algorithm for stuck faults. A novel fault injection technique is pro- posed. Experimental results show that neither a comprehen- sive functional verification sequence nor a test sequence gen- erated by a sequential circuit test generator for stucck-at faults produces a high fault coverage for transition faults. and finite state machine (FSM) synthesis for delay testabil- ity was adtlressedl. A known reset state is required. The method has limited capability of handling large circuits, because it Icquires the extraction of the complete or partial state transition graph. The approach suggested in 1131 assumes that the circuit is fault-free in the initialization and fault propagation phases. This suggestion is valid if the clock is applied alt a lower speed during the initialization and the fault propagation phases and is applied at a rated speed during the fault activation phase. Slow clock for ini- tialization ,and fault propagation is also assumed in (12). To the author's Icnowledge, no delay-fault simulator €or sequential circuits has been reported before. In this paper, we address the problem of simulating transition faults in sequential circuits. We first enhance the transition fault model for the gate-delay faults and the stuck-open faults in synchronous sequential circuits. We assume the input vectors and clock are applied at speed and at a fixed interval during test application. The primary outputs are: also observed at a fixed interval. We use a transition fault of size n clock cycles to model the defects that cause im extra delay of n clock cycles to a transition. We present a fault simulation algorithm for the proposed fault model. Fault simulation results on the ISCAS-89 sequential benchmark circuits are presented in Section 5.

This paper addresses the performance optimization problem for sequential logic circuits. It is shown how the notion of false paths, traditionally defined for combinational logic circuits, can be extended to the sequential context by considering the operation of the circuit over multiple clock-cycles. These multicycle false paths can be removed from the circuit using techniques similar to those proposed for combinational logic circuits. This observation offers new techniques to improve the performance of sequential logic circuits. An implementation of an algorithm that uses these ideas shows significant performance improvement on some typical benchmark circuits at a modest area overhead.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A methodology for the redesign of sequential VLSI circuits to increase the circuit speed involves cascading the circuit over a plurality of time frames without the memory elements, identifying any long false paths in the cascaded circuit, reconfiguring the original circuit to eliminate the false paths while providing fanout to preserve functionality, and retiming the reconfigured circuit to reduce circuit delay.

TPG for synchronous sequential circuits has received wide attention over the last two decades, yet unlike for (full-scan) combinational circuits, for many sequential benchmark circuits 100% fault efficiency still cannot be reached. This illustrates the complexity of sequential circuit ATPG. The huge search space, which exists during sequential circuit TPG, is the main reason for this complexity. Powerful techniques and heuristics are required to cope with this search space. One way to reduce the search space is the detection of illegal states. These states cannot be justified with an initialization sequence. In this paper, we propose new techniques to find illegal states and to remove the over-specification of these states by searching common fractions in the list of illegal states. Experimental results demonstrate the importance of an as complete as possible illegal state list: Higher fault efficiencies are reached for the sequential ISCAS'89 circuits (1989) and industrial circuits, together with a large reduction of CPU time.

In this paper, a time and memory-efficient diagnostic fault simulator for sequential circuits is first presented. A distributed diagnostic fault simulator is then presented based on the sequential algorithm to improve the speed of the diagnostic process. In the sequential diagnostic fault simulator, the number of fault-pair output response comparisons has been minimized by using an indistinguishability fault list that stores the faults that are indistinguishable from each fault. Due to the symmetrical relationship of the fault-pair distinguishability, fault list sizes are reduced. Therefore, the different diagnostic measures of a given test set can be generated very quickly using a small amount of memory. To further speed up the process of finding the indistinguishable fault list for each fault, a distributed approach is proposed and developed. The major idea for this approach is that each processor constructs the indistinguishable fault lists for a certain percentage of faults only. Experimental results show that the sequential diagnostic fault simulator runs faster and uses less memory than a previously developed one and that the distributed algorithm even achieves superlinear speedup for a very large sequential benchmark circuit, s35932. To the authors' knowledge, no distributed diagnostic fault simulation system for sequential circuits has been proposed before.

State assignment is the most critical step in the synthesis and optimization of sequential circuits as it significantly impacts sequential circuits area and power. Due to the high complexity of the state assignment problem and the ineffectiveness of existing deterministic algorithms in generating good solutions, evolutionary algorithms can be employed to obtain more effective state assignment solutions. In this paper, we propose a probabilistic tabu search (PTS) state assignment algorithm that is employed for the optimization of area and power of sequential circuits. The proposed algorithm is based on tabu search with the addition of exploiting code swap probabilities to prune the search space more effectively. Code swap probabilities are updated dynamically during the execution of the algorithm in such a way that code swaps that result in relatively inferior solutions will be assigned lower probabilities while those that result in good solutions will be assigned higher probabilities. In addition, tabu list size is changed dynamically during execution to help the algorithm get out of local minima. Based on experimental results, we show that the proposed PTS state assignment algorithm is more effective than all existing state assignment algorithms as it generates state assignment solutions with significantly lower area and power.

In sequential circuits, the current output can depend on both past and current inputs. However, certain kinds of sequential circuits do not refer to all of the past inputs to generate the current output; but only to a subset of past inputs. This paper investigates which subset of past inputs a sequential circuit refers to, and proposes a new classification of sequential circuits based on this criterion. While the conventional classification of sequential circuits distinguishes between synchronous and asynchronous circuits, the new classification consolidates synchronous circuits and multiple clock domain circuits into the same category. This is consistent with the notion that “multiple clock domain circuits are analogous to synchronous circuits,” and thus, the proposed classification appears valid from this perspective. It is expected that a method underlying our classification will allow a deeper understanding of sequential circuits.

In this paper we present an efficient technique to reduce the power dissipation in a technology mapped CMOS sequential circuit based on logic and structural transformations. The power reduction is achieved by adding sequential redundancies from low switching activity gates to high switching activity gates such that the switching activities at the output of the connected to gates are significantly reduced. We show that the power reducing transformations result in a circuit that is a valid replacement of the original. The notion of validity used here is that of a delay safe replacement, i.e., the original circuit and the transformed circuit cannot be distinguished by observing the input and output behavior as long as the transformed circuit is clocked a finite number of cycles before applying any useful inputs. The potential transformations are found by direct logic implications applied to the circuit netlist. Therefore the complexity of each individual transformation is polynomial in the size of the circuit, allowing the processing of large designs.

This paper presents an efficient and accurate Monte-Carlo approach to the problem of estimating average node switching probabilities in sequential circuits which are used in average power estimation and reliability analysis of these circuits. Specific error bounds for the proposed estimation method are given at a certain level of confidence. This method is based on the analysis of paths in the State Transition Graph (STG) of the circuit and is validated by both theoretical analysis as well as experimental results.

In signature analysis, aliasing is usually examined under the independent or the q-ary symmetric error model. In contrast to the independent error model, the q-ary error model assumes space correlation among outputs. However, both independent and q-ary error models assume that the errors resulting from consecutive test vectors are independent over time. This assumption is reasonable for combinational circuits but certainly unrealistic for sequential logic circuits as the outputs of a sequential circuit depend on the previous state as well as the current input vector. For this reason a new error model, called the generalised time dependent q-ary (GTDQ) error model, is proposed. This error model extends the q-ary error model to consider both space and time correlation. A second parameter c is used to model the time correlation. By modelling the signature analyser as a Markov process the authors obtain a closed form expression for exact aliasing probability for arbitrary test length for a class of multiple-input linear automata signature registers (MILASRs). An easily verifiable criterion is given to determine whether a MILASR falls into this category. Finally, experimental results are provided for some real sequential circuits to validate the proposed error models.

A description is given of SIS, an interactive tool for synthesis and optimization of sequential circuits. Given a state transition table or a logic-level description of a sequential circuit, SIS produces an optimized net-list in the target technology while preserving the sequential input-output behavior. Many different programs and algorithms have been integrated into SIS, allowing the user to choose among a variety of techniques at each stage of the process. It is built on top of MISII and includes all (combinational) optimization techniques therein as well as many enhancements. SIS serves as both a framework within which various algorithms can be tested and compared and as a tool for automatic synthesis and optimization of sequential circuits. >

Power estimation for CMOS sequential circuits is difficult because of sequential feedback loops embedded in the circuits. This paper presents a new method which applies probabilistic propagation and an iteration method to obtain the transition probability of circuit internal nodes. The time and space complexity of computation is improved by compacting the circuit before calculation. Experimental results show that our method is applicable even for large sequential circuits.

Small, low-cost embedded systems implemented as sequential circuits often do not contain scan chains. Malicious trojan circuits, which themselves may be state machines, inserted into such systems are hard to detect. We present an effective methodology to detect sequential trojan circuits inserted into sequential hardware designs without scan chains. The methodology consists of three steps: We use sequential testability metrics, model checking and signal tracing to progressively separate the trojan gates from legitimate circuit gates. We show experimental results demonstrating the effectiveness of the methodology using several test cases.

The advantage of Evolvable Hardware over the traditional circuit design approach is its capacity for dynamic and autonomous adaptation. EHW can reconfigure its structure according to changes in the task requirement or the environment in which the EHW is embedded. Focuses on the application of extrinsic evolution and their used for the design of small sequential circuits. At the foundation of evolvable hardware, a full-connected feed-forward circuit network model was constructed which is based on the character of sequential circuits. This model is imitating the structure of artificial neural network. It firstly using D flip-latch and logic gate as the basic element, and the one-to-one mapping existed in the mathematical encoding, circuit topology, and HDL file was established. Then, the method to obtain HDL file according to circuit encoding was designed, the circuit evaluation process was automated by using of batch processing technology. Designed the mutation rate dynamic adjust function to improve the performance of (1+λ)-ES. Experiment results of two types of Finite State Machine proved the feasibility and validity of the circuit evolution method.

Test Pattern Generation (TPG) for sequential and/or 3-state circuits involves two important aspects which often are handled incorrectly: bus conflict detection and completeness of search in TPG. The correct handling of both aspects strongly depends on the signal model used by TPG. We propose a novel, set-based, signal model using the power-set (i.e., the set of all possible subsets) of the basic values {0, 1, Z}. TPG using this signal model guarantees complete search, provides exact bus-conflict detection, and is more efficient than TPG using the traditional signal models for J-state and sequential circuits. Experimental results demonstrate this by higher fault efficiencies combined with a large reduction of backtracking and computing time for sequential ISCAS'89 and industrial circuits.