Power Optimization Based on Link Breaking Methodology

The reliability of automatic control systems depends on the reliability of its elements in particular computing equipment. Computing equipment is a constant consumer of power from the network During the operation of computing technology, there are often dynamic changes in the voltage in the power supply network-dips and interruptions. Dips and interruptions are one of the main problems in terms of noise immunity of computing equipment. The results of studies of the noise immunity of computing equipment with dynamic changes in the power supply voltage are article presents.

A bandgap voltage reference in a GaAs heterojunction bipolar transistor process is analysed and designed. The design provides an on-chip reference intended for use with more complex integrated circuits designed in this HBT process. Key design parameters of the HBT bandgap reference are presented and compared to a classical silicon bandgap reference. A practical operational amplifier for the reference is also presented. The prototype reference achieves a temperature coefficient of 7 ppm/°C over a temperature range of 0°C to 100°C. The voltage reference changes are measured at 0.1% with power supply voltage changes of ± 0.2 V.

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

BackgroundElectrospinning is an effective method for producing high-quality biopolymer nanofibers, such as cellulose and chitosan. Cellulose nanofibers have excellent mechanical properties and biocompatibility, making them a promising material for tissue engineering. Chitosan nanofibers are biodegradable, biocompatible, and antimicrobial, making them ideal for biomedical applications. The electrospinning parameters, including solution concentration, power supply voltage, orifice diameter, temperature, humidity, and flow rate, play a crucial role in determining the nanofiber diameter, morphology, and mechanical properties, as well as their suitability for various applications. ObjectiveThis systematic review aims to synthesize and evaluate the current evidence on the influence of electrospinning parameters on the production and properties of cellulose and chitosan nanofibers. MethodsA comprehensive search of electronic databases was conducted to identify relevant studies. The inclusion criteria were studies that investigated the effect of electrospinning parameters on cellulose and chitosan nanofibers. ResultsIt was found that for cellulose, the average fiber diameter increased with increasing each of solution concentration, power supply voltage, orifice diameter, temperature, and humidity. Contrary to tip - collector distance and some optimal points in temperature, where average fiber diameter decreased. For chitosan, the change in voltage and tip to collector distance did not alter the average fiber diameter except for some readings of voltage, which behaved differently. On the other hand, the average fiber diameter increased with increasing flow rate. ConclusionThe review highlights the importance of considering electrospinning parameters in the production of high-quality biopolymer nanofibers and provides insights into the optimization of these parameters for specific applications. This review also highlights the need for further research to better understand the underlying mechanisms of electrospinning and to optimize the process to produce biopolymer nanofibers with improved properties.

A low-voltage, two-stage ring voltage-controlled oscillator (VCO) which can tolerate temperature variation is presented in this paper. Designed using a 0.13 μm CMOS technology, this VCO is capable of operating at 1-V power supply voltage not only for low power consumption, but also to reduce hot-carrier effects and improve reliability and lifetime. It incorporates coarse and fine frequency tuning mainly for tolerance of process variations while achieving small control-voltage-to-frequency gain and enough tuning range of the VCO. Most importantly, a new temperature compensation technique which is suitable for low power supply voltage design is proposed to enable continuous operation of the VCO in variable ambient temperatures environment. Simulations show that with the proposed techniques, the VCO can tolerate process variations, dynamically adapt to different temperatures, and achieve a low temperature sensitivity of 34 ppm/°C over the range from −40°C to 120 °C.

This paper presents a novel combination of two fully integrated phase-locked loops (PLLs) to control the oscillation frequency and modulation frequency of a switched injection-locked oscillator (SILO). The SILO is used as an active reflector transponder in a frequency-modulated continuous wave (FMCW) radar system. A fractional-N PLL (RF-PLL) with a tri-state phase-frequency detector (TSPFD) sets the oscillation frequency of the voltage controlled oscillator (VCO) to 2.45 GHz. Another integer-N PLL (modulation PLL) switches the tail current source of the VCO to achieve SILO behavior at the time when the RF-PLL is not controlling the VCO. The RF-PLL supports division ratios from 64 to 511 with a frequency resolution of 0.2 Hz. Reference spur levels are below -48 dBc while the out-of-band phase noise is -103 dBc/Hz at a 1MHz frequency offset. The modulation PLL is based on a Maneatis-cell ring-oscillator supporting modulation frequencies between 6MHz and 20 MHz. Furthermore, the duty cycle of the modulation signal can be set in steps of 0.8 %. Due to the novel TSPFD, the oscillation frequency of the SILO changes only by 36MHz within 10 minutes when the RF-PLL is inactive. The complete circuit is manufactured in a 180nm SiGe BiCMOS process and consumes a total power of 128mW.

4 - 2-Wire virtual remote sensing for voltage regulators: Clairvoyance marries remote sensing

Voltage controlled oscillators (VCOs) implemented in digital VLSI IC (integrated circuit) technology typically have very poorly controlled centre frequencies and poor phase noise characteristics, thus severely limiting their use in phase locked loop (PLL) applications. The new technique presented incorporates an accurate local reference frequency into the PLL structure. The key parameters of the new PLL structure are identified and the performance characterised. It is shown that the range of frequencies to which the new PLL structure can lock can be confined to a small region around the accurate local reference frequency. It is also shown that the new PLL structure provides other benefits such as a reduction of the VCO phase noise, allowing poor quality VCOs to be used in demanding applications. The new technique does not require any monitoring nor any switching of the local frequency reference signal which is always acting.

A radiation-hardened-by-design (RHBD) phase-locked loop (PLL) designed in 0.13-μm CMOS is demonstrated to effectively mitigate the single-event transient (SET) effect. In this paper, a novel Current Limiter circuit Controlled by Comparators (CLCBC) is proposed to improve SET tolerance of the Charge-Pump (CP). Further a SET tolerant Voltage-Controlled Oscillator (VCO) based on an interleaved architecture is also presented. The CLCBC features in being able to detect the abnormal current surged at the CP output node as a result of a SET strike and then to keep this abnormal current from flowing into the low pass filter (LPF) by a high resolution and fast compensation scheme. The VCO consists of a 4-stage interleaved delay buffer implemented to perform the Majority Decision Voting functions without incurring additional signal delay. Such a VCO can generate symmetric multi-phase outputs. Simulation results show that, with deposited charges of 2650fC, the output variation of the CP/ LPF hardened by the proposed CLCBC is reduced by 84.5%, in comparison to the previous work. For the RHBD PLL designed, the perturbation of the VCO control voltage is reduced by 95.6%, while the PLL recovery time is reduced by 68.9%, and the period variation range of the output is reduced by 97%, all with reference to the baseline PLL unhardened. Moreover, the jitter performance of the proposed RHBD PLL remains unaffected and is nearly the same as that of the baseline PLL unhardened.

In this paper, an enhanced voltage controlled oscillator (VCO) at center frequency 125 GHz with tuning rang of 24% is presented. The proposed idea is based on the tuning capacitance using MOS varactor. The structure is consisted of applying an MOS varactor capacitor to the drain and bulk (in parallel) of NMOS transistor in 65 nm CMOS standard technology. The obtained output of the proposed VCO at 2nd harmonic is tunable at 110–140 GHz frequency with applying ± 1.2 input tuning voltage. Simulation results of the proposed circuit are obtained after extracting post layout (with total chip size of 0.07 mm2) and confirm theoretical results. Compared to the resent designs, the obtained results indicate that the proposed circuit has high tuning range, low die area and a good figure of merit @ 1.2 power supply voltage.

The Costas loop can be considered an extension of the phase-locked loop (PLL). The PLL, invented 1932 by French engineer Henri de Belleszice, was first used for the synchronous reception of amplitude modulated radio signals with carrier (c). If the modulation index is less than 100%, the modulated signal is always in phase with the carrier signal (c), irrespective of the polarity of the modulating signal. The PLL then reconstructs a local carrier (loc) that is in phase the carrier (c) of the AM signal. The modulating signal is recovered by multiplying the AM signal with the local carrier (c) with subsequent lowpass filtering. This method of synchronous reception fails, however, when an AM signal with suppressed carrier is transmitted. Here the modulated signal is in phase with the (suppressed) carrier when the modulating signal is positive, but it is in antiphase with the carrier when the modulating signal is negative. When this AM signal is fed to the input of a PLL, it would create a local carrier (loc) that is in phase with the carrier when the modulating signal is positive, but in antiphase with the carrier when the modulating signal is negative. Recovery of the modulating signal is therefore not possible. The situation would be the same when the transmitted signal is a Binary Phase Shift Keying (BPSK) signal, a Quadrature Phase Shift Keying (QPSK) signal, or a Quadrature Amplitude Modulation (QAM) signal. This problem has been solved by the invention of the Costas loop by American engineer James P. Costas in 1956. The Costas loop is able to lock onto a modulated signal also in cases where the carrier is suppressed. When we compare the topology of a Costas loop with that of a PLL, we recognize that the PLL is built up from a cascade of three circuits: (1) a phase detector, (2) a loop filter, and (3) a voltage-controlled oscillator (VCO). There is a feedback path from the output of the VCO to the input of the phase detector. In case of the PLL, the input signal is propagated through this cascade of three blocks. There is only one signal path in the PLL. In contrast, there are two signal paths in the Costas loop: (1) a so-called “I branch” (in phase), (2) a so-called “Q branch” (quadrature phase). It is shown that with that configuration the loop is able to create a local carrier that is correctly locked to the carrier of the received signal even in cases when the carrier is suppressed. The invention of the Costas loop had a dramatic impact on any kind of communication receivers; one or more Costas loops are found in TV, radio, satellite communications, mobile phones, modems, etc.

A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The measurement results show that the PLL achieves a phase noise of -85dBc/Hz in band and -112dBc/Hz at 10-MHz offset from the carrier frequency of 24GHz. The whole chip occupies an area of 1.3 × 0.8mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 36-mW from a 1.2-V supply voltage (a 0.8-V supply voltage for VCO) excluding output driving buffers.

This paper presents a high-speed, broadband phase -locked loop (PLL) for RF transceiver in 65nm CMOS process. Programmable structures are used to improve the lock speed of the PLL, the charge pump and loop filter can be adjusted by digital bit to reduce locked time of PLL. An integrated voltage-control oscillator (VCO) with 75% tuning range and a high-speed divider are used to accomplish all the frequencies. To achieve a wide tuning range while keep a low gain and a low phase noise, the VCO uses switched capacitor array. Finally, the PLL realizes 6-12 GHz wide frequency coverage. The phase noise performance at 6GHz is -113dBc/Hz@lMHz. The layout area is only 0.5265mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Working at 1. 2V supply voltage, the power consumption of the circuit is 11.3432 mW. The lock time of the PLL after using AFC is about 15. 258us.

Many of today's applications require that a phase-locked loop (PLL) operate at high speeds, while maintaining reasonable phase noise and jitter performance. Voltage-controlled oscillators (VCO) are important building blocks in PLLs. More importantly, the VCO is the major contributor of phase noise in a PLL. The noisy environment, mainly due to the switching noise generated by the digital portion of these systems. imposes stringent constraints on the design of VCOs, especially phase noise or timing jitter. The switching noise originated in the digital portion of the systems are coupled to the supply and ground rails of the VCO of PLLs. Another important block of a PLL is the charge-pump, a block that is responsible for generating the control voltage to be applied to the VCO. The stability or fluctuation of the control voltage, can severely affect the phase noise performance of the VCO. The research in this thesis, centered on (i) the design considerations of CMOS charge-pumps, (ii) the timing jitter of the delay-cells of low-voltage CMOS ring-VCOs and (iii) the design of a high-speed ring oscillator. A PLL was designed using a new active inductor 6.3-GHz ring oscillator, with a tuning range of +/- 15% was designed in 0.18um CMOS technology. The ring oscillator employed active inductor loads that resulted in an improvement of about 42% in oscillation frequency when compared to the conventional resistor loaded ring oscillator.

Design of a stable Phase Locked Loop (PLL) working in MHz frequency range is proposed. Focus of this work is to achieve a symmetric design, where rise and fall time are equal for low operating frequencies. All the blocks of PLL i.e Phase Frequency Detector (PFD), Charge Pump and Loop Filter (CPLF), Voltage Controlled Oscillator (VCO) and Frequency Divider (FD) are carefully designed and integrated. PFD is implemented using D flip-flop and is made to detect minimal phase errors. CPLF has differential design for noise immunity and for avoiding floating conditions. The 15 stage VCO gives frequency range of 30 MHz to 200 MHz for input voltage range of 0.5 V to 1.05 V with a resistor for optimizing linearity. The integrated PLL is stable in the output frequency range of 44 MHz to 200 MHz for given input frequency range of 11 MHz to 50 MHz. The designs are implemented in 180 nm technology and for a supply voltage of 1.8 V.