Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

With the increase of the number of IP cores integrated in SOC, the functions of SOC ar e becoming more complexed. Test time and test cost grow rapidly, therefore it becomes bo ttleneck of SOC test. Test scheduling is one of the efficient approaches to solve the forenamed ques tion. Cross-entropy method, which is ba sed on probability density function, has been used to solve the SOC test scheduling problem. Experimental results on ITC’02 benchmarks show that the proposed method provides better test time results compared to the Linear-Programming. Keywords: System on chip, test scheduling, cross-entropy method 1. INTRODUCTION In order to shorten the time to market, core based system-on-chip (SOC) design has becomed a widely used technique of integrated circuit design. Compared with system-on-board, work frequency of SOC has improved observably because signal transfers delay is avoid. However, the testing of SOC and the reusable cores becomes a bottleneck of the SOC development. The SOC test includes test information exchange mechanism, test wrapper generation, test access mechanism (TAM) design, test controller design, test schedulin g and test integration, etc. Among the SOC test issues, the test scheduling is one of the most important challenges. Many works have forced on core test scheduling to minimize the overall testing time, in [7], the test scheduling is mapped to the linear programming (LP) problem, but the computation time is too long. In this paper, we use a cross-entropy (CE) method, which is based on probability density function, to solve the test scheduling problem. The paper is organized as follows. In section II, the test scheduling problem is briefly described. We formulate the problem of test scheduling using CE method in section III. Experimental results are given in section IV, and section V concludes the paper.

In this paper, we consider a cellular/infostation integrated network that supports on-demand data service delivery over a wireless link to users in a high-speed train. For the requests with different lifetimes and prices that they are willing to pay, we develop the optimal packet schedule that aims at earning the maximum revenue. To this end, we formulate the problem as an integer linear program (ILP). The problem cannot be solved efficiently by existing ILP solvers with guaranteed polynomial-time complexity in the worst case. By exploring the special structure of the formulated ILP, we propose a novel Checker algorithm and prove that this algorithm is guaranteed to find the offline optimal schedule in polynomial time. Based on the relevant insights, we further develop a class of online Checker algorithms that require only causal knowledge of service demands and wireless channel capacities. It is established that these online algorithms have a worst-case competitive ratio of 1/2, i.e., total revenue earned by them is at least half as much as the revenue earned by an offline optimal schedule that knows the complete a priori knowledge of future requests and channel conditions. Simulation results are provided to demonstrate the merit of the proposed algorithms.

System on a chip (SOC) based on reusable IP core has been widely used in integrated circuit (IC) design and manufacturing. However SOC efficient test is still the bottle-neck issue. Test scheduling can enhance parallel test to minimize test application time at SOC system level. We present a modified differential evolution (MDE) approach to solve the problems of test scheduling and test access mechanism (TAM) partition for system on chips. A new hybrid mutation mechanism based on the probability estimation operator is introduced in the paper for better handling test scheduling, where the first variation coefficient stays the same but the second variation coefficient changes with iterative times. The different evolutionary strategies are adopted to accelerate effectively convergence without loss in population diversity as far as possible. Different mutation operators and evolutionary strategies are combined to get optimal results. The experimental results on ITC'02 SOC benchmarks are encouraging compared with the improved quantum-inspired evolutionary (IQI), genetic algorithm (GA), the integer linear programming formulation (ILP) and heuristic approaches.

In this paper, we propose an efficient scheduling algorithm for problems in which tasks with precedence constraints and communication delays have to be scheduled on an heterogeneous distributed system with one fault hypothesis.Our algorithm combines the DSS_OPT algorithm and the eFRCD algorithm. To provide a fault-tolerant capability, we employ primary and backup copies. In this scheme, backup copies can overlap other backup copies, and backup copies are not established for tasks that have more than one primary copy. The result is a schedule in polynomial time that is optimal when there is no failure, and is a good resilient schedule in the case of one failure.

The test scheduling problem is one of the major issues in the test integration of system-on-chip (SOC), and a test schedule is usually influenced by the test access mechanism (TAM). In this paper we propose a graph-based approach to power-constrained test scheduling, with TAM assignment and test conflicts also considered. By mapping a test schedule to a subgraph of the test compatibility graph, an interval graph recognition method can be used to determine the order of the core tests. We then present a heuristic algorithm that can effectively assign TAM wires to the cores, given the test order. With the help of the tabu search method and the test compatibility graph, the proposed algorithm allows rapid exploration of the solution space. Experimental results for the ITC02 benchmarks show that short test length is achieved within reasonable computation time.

We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of test resources (e.g., test access mechanisms (TAM)), we determine the test plan for the application of the tests to the SOC. Test planning in this paper refers to the combined activities of test access architecture partitioning and test scheduling. These activities must be performed in conjunction as the choice of the test access architecture influences the test schedule. We justify the formulation of test scheduling w.r.t. minimum average completion time criterion as compared to minimum makespan. We show that then the problem of scheduling tests on TAMs can be mapped onto a graph theoretic problem which has a polynomial time optimal solution. We have implemented our algorithm as a test planner tool TPLAN. We present the theoretical analysis of our approach in this paper, and compare our results against those published earlier using integer linear programming techniques with encouraging results.

We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.

The main scope of this paper is the implementation of a method for production scheduling, using advanced model checking tools. This method makes use of timed automata to model complex production scheduling problems such as the job-shop and the open-shop scheduling problems. By modelling scheduling problems using timed automata, feasible schedules correspond to paths in the automata, while finding the optimum schedule corresponds to finding the shortest path in an automaton. Several algorithms and heuristics have been proposed for finding the shortest paths in timed automata, which are mainly based on the implementation of graph algorithms that search the transition graph. In our work, an advanced model design and checking tool, called UPPAAL, has been used to implement and test the above method on a number of different models and to show the effectiveness of such an approach in terms of finding optimal or near to optimal, schedules in polynomial time, even for large-scale problems.

Preemptive scheduling of independent jobs on parallel machines subject to financial constraints

On the optimal scheduling of periodic tests and maintenance for reliable redundant components

In this paper, we propose a new data structure called dual sequences to represent SOC test schedules. Dual sequences are used together with a simulated annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test schedules for SOCs and minimizing tester memory and test channels. Results of experiments conducted on ITC’02 benchmark SOCs show the effectiveness of the proposed method.

ABSTRACTA given number of jobs in an open shop scheduling environment must each be processed for given amounts of time on each of a given set of machines in an arbitrary sequence. This study aims to achieve a schedule that minimizes total weighted completion time. Owing to the strong NP-hardness of the problem, the weighted shortest processing time block (WSPTB) heuristic is presented to obtain approximate solutions for large-scale problems. Performance analysis proves the asymptotic optimality of the WSPTB heuristic in the sense of probability limits. The largest weight block rule is provided to seek optimal schedules in polynomial time for a special case. A hybrid discrete differential evolution algorithm is designed to obtain high-quality solutions for moderate-scale problems. Simulation experiments demonstrate the effectiveness of the proposed algorithms.

Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given, the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space, and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can solve the problem of test scheduling effectively.

Global scheduling of real time tasks with precedence constraints has received significant attention recently. Specifically, on multiprocessor systems, the directed acyclic graph (DAG) model well-represents parallelizable workloads with precedence constraints. Hence, many studies have recently been published analyzing DAG structures using decomposition and window-based analysis methods. We identified a set of schedulable DAG taskets that are hard-to-analyze using state-of-the-art window-based schedulability tests. Additionally, we observe that the window-based test solely depends on one structural feature of the DAG taskset, which raises concerns about its pessimism in many settings. In this paper, to address these concerns, for hard real-time sporadic implicit-deadline DAG tasksets, we perform LAG-based schedulability analysis, which offers a more holistic view of the taskset than the window-based analysis. We present a companion utilization-based schedulability test to the state-of-the-art, which considers additional structural features of DAGs. Our results show that by considering such features, our LAG-based test empirically dominates the state-of-the-art test on over 80% of the evaluated DAG tasksets. Moreover, combining our LAG-based test in conjunction with the window-based tests can achieve high schedulability in many cases.