Optimizing SOC Test Resources Using Dual Sequences

Test scheduling is a major problem in system-on-a-chip (SOC) test automation. We present an integrated framework that addresses several important test scheduling problems. We first present efficient techniques to determine optimal SOC test schedules with precedence constraints, i.e., schedules that preserve desirable orderings among tests. We then present a new algorithm that uses preemption to obtain optimal test schedules in polynomial time. Finally, we present a new method for determining optimal power-constrained schedules. Experimental results for a representative SOC show that test schedules can be obtained in reasonable CPU time for all cases.

Network-on-chip (NoC) is an emerging design paradigm intended to cope with future systems-on-chips (SoCs) containing numerous built-in cores. Since NoCs have some outstanding features regarding design complexity, timing, scalability, power dissipation and so on, widespread interest in this novel paradigm is likely to grow. The test strategy is a significant factor in the practicality and feasibility of NoC-based SoCs. Among the existing test issues for NoC-based SoCs, test access mechanism architecture and test scheduling particularly dominate the overall test performance. In this paper, we propose an efficient NoC-based SoC test scheduling algorithm based on a rectangle packing approach used for current SoC tests. In order to adopt the rectangle packing solution, we designed specific methods and configurations for testing NoC-based SoCs, such as test packet routing, test pattern generation, and absorption. Furthermore, we extended and improved the proposed algorithm using multiple test clocks. Experimental results using some ITC’02 benchmark circuits show that the proposed algorithm can reduce the overall test time by up to 55%, and 20% on average compared with previous works. In addition, the computation time of the algorithm is less than one second in most cases. Consequently, we expect the proposed scheduling algorithm to be a promising and competitive method for testing NoC-based SoCs.

We propose an SOC test scheduling method based on simulated annealing. In our method, the test scheduling is formulated as a two-dimensional bin packing problem (rectangle packing) and a data structure called a sequence pair is used to represent the placement of the rectangles. Simulated annealing is used to find the optimal test schedule by altering an initial sequence pair and changing the width of the core wrapper. We also propose a method of wrapper design for cores without internal scan chains. Experiments are conducted on ITC'02 benchmarks, showing that overall the proposed method provides better solutions compared to earlier methods.

This paper presents a novel approach for selecting optimal pseudo random and deterministic test patterns and minimizing test time for multi-clock domain SoCs based on a hybrid BIST architecture for each core. For test scheduling, a concurrent method considering peak power upper bound is used. A test scheduling graph is presented for modeling concurrent hybrid BIST test scheduling. Furthermore, a heuristic is proposed for selecting cores to be tested concurrently and the order of applying sequence of test patterns to each core. Experimental results show that the proposed heuristics for both selecting groups of cores to be tested concurrently during the SoC test process, and determining the amount of deterministic and pseudo random test patterns for each core, give us an optimized method for multi clock domain SoC testing compared with the existing methods.

Test scheduling for core-based SoCs is a challenging problem. Test schedules must be crafted with the objectives of minimizing testing time and ATE vector memory requirements, to reduce test cost, under the constraints of total available test access mechanism (TAM) width. Prior research in test scheduling has mainly used search procedures like ILP and rectangle packing to solve this problem, but these approaches are inherently computationally expensive. In this paper we describe a novel algorithm to solve the test scheduling problem using a combination of network flow algorithms, malleable job scheduling and reconfigurable wrapper design. Our approximation algorithm has polynomial time complexity and produces schedules close to the theoretical lower bound. Extensive experimental results using the new ITC'02 SoC benchmarks validate the quality of our solutions.

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

Overheating has been acknowledged as a major issue in testing complex SOCs. Several power constrained system-level DFT solutions (power constrained test scheduling) have recently been proposed to tackle this problem. However, as it will be shown in this paper, imposing a chip-level maximum power constraint doesn't necessarily avoid local overheating due to the non-uniform distribution of power across the chip. This paper proposes a new approach for dealing with overheating during test, by embedding thermal awareness into test scheduling. The proposed approach facilitates rapid generation of thermal-safer test schedules without requiring time-consuming thermal simulations. This is achieved by employing a low-complexity test session thermal model used to guide the test schedule generation algorithm. This approach reduces the chances of a design re-spin due to potential overheating during test.

Partial-intrusion BIST reduces area overhead and increases chip performance by reducing the number of test registers, but it requires a test schedule definition. The scheduling of the tests impacts directly the test application time. This paper presents a novel model of the test plan scheduling problem for partial-intrusion BIST circuits. Test application time is reduced by performing scheduling to allow the execution of test plans in a pipelined fashion. Test scheduling conflicts are avoided by exploiting the parallelism which is revealed by a flexible test representation; consequently, test concurrency is increased. Computational efficiency is gained by performing incremental, subtractive heuristic test scheduling decisions. The effects of each test decision are rigorously propagated, limiting the test scheduling possibilities to only those which lead to a feasible scheduling solution. Experimental results show that high levels of test concurrency are achieved in a computationally efficient manner by limiting the state of the scheduling search space using conflict probability estimation and rigorous pruning of infeasible test options. >

Increased core test parallelism translates into reduced SOC test application time; yet the availability of a limited number of tester channels hampers this parallelism. Furthermore, the test vectors to be delivered into core scan chains need to be stored in the tester memory, imposing considerable costs on SOC tests. We propose an SOC test methodology delivering all the benefits of core self-test, while ensuring fault coverage levels identical to those attained in deterministic test. In the proposed methodology, a single LFSR broadcasts pseudo-random patterns to each core; the LFSR patterns are transformed into the actual test vectors of a core while they are being shifted into the core scan chain. The transformation is realized through the logic gates inserted between the core scan cells. The efficacy and the cost-effectiveness of the proposed methodology reflects into significantly reduced test costs.

SummaryModern power systems are being shifted its attention towards distributed generations (DGs). DGs have allured more concern as an auspicious opportunity with considerable economic profits. To minimize the power generation costs of DGs, day‐to‐day operation scheduling is essential. The role of this study is to offer an optimal operation schedule for DG with several energy sources including renewable energy sources (RES), considering economic facets. In order to achieve the cost minimization along with optimal scheduling, an objection function has been formulated and solved using the optimization algorithms. This study aims to present the applications of differential evolution (DE) algorithm and its variants such as opposition‐based differential evolution (ODE), self‐adaptive differential evolution (SaDE), improved differential evolution (IDE), and cultivated differential evolution (CuDE) for scheduling DG optimally. A scheme for optimal scheduling of thermal, wind power, and solar PV generators has been evaluated. The simulations have been carried out on IEEE 14 bus system, IEEE 30 bus system, IEEE 57 bus system, and Tamil Nadu Generation and Distribution Corporation Limited (TANGEDCO), as a real part of 62 bus Indian utility system (IUS). The novelty of this study lies in simulating a real‐time system for solving optimal scheduling problem, in that way helping decision makers to choose the optimal operation points. The results indicate that the SaDE outperformed other DE variants by giving the best fitness value and convergence rate.

Both wrapper and TAM are important components in SOC test architecture, and wrapper scan chain optimization and TAM optimization are NP-hard problems. Addressing wrapper scan chain optimization or TAM optimization separately leads to SOC test time sub-optimal. This paper presents a TWC&S (TAM/wrapper co-optimization and scheduling) algorithm for multi-clock SOC after combining the advantages of wrapper scan chain optimization and TAM optimization, and it aims to decrease test time of multi-clock SOC extremely. To demonstrate the validity of the proposed algorithm, experiment is performed on the multi-clock SOC MCDS 2 . The results show that there exist inflexion of test time, and the optimal test time is 23.2% when the widths of test bus are 20 vs. the least one. The phenomenon, decreasing degree of test time decreases slowly with test bus widths increase, demonstrates that trade-off will be achieved properly among test time, test area and design complexity.

Optimal Short-Term Scheduling for Cascaded Hydroelectric Power Systems considering Variations in Electricity Prices

On the optimal scheduling of periodic tests and maintenance for reliable redundant components

We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.

Test scheduling is an important task for the test of a system on chip, and it determines the assignment of cores to the test access mechanism such that the overall test time is minimized. A new test scheduling approach based on cultural algorithms for system on chip is presented in this paper. First of all, the optimization model of test scheduling is given, the model uses the information such as the bits width of the test access mechanism and the scale of test sets of cores, the crosstalk fault test sets of core interconnect lines is also discussed. Secondly, a method based on cultural algorithms is proposed to solve the optimization model of test scheduling. The ant colony algorithm is used in the population space, and the conventional genetic algorithm is used in the belief space. The feasible solutions of test scheduling are represented by individuals, a lot of individuals form the populations. The optimal test scheduling scheme is obtained by the evolution of the populations. Experimental results on a lot of benchmark circuits show that the proposed approach in this paper can solve the problem of test scheduling effectively.