Precise miss analysis for program transformations with caches of arbitrary associativity

A 3D Free Surface Flow and Transport Model on Different High Performance Computation Architectures

This document presents key principles and practical considerations for optimizing CPU-bound code in the context of high-performance scientific computing. While classical algorithmic complexity provides a hardware-independent framework for evaluating scalability, real-world performance is largely determined by low-level factors such as memory access patterns, cache behavior, data locality, and compiler optimizations. The discussion highlights how modern architectures rely on hierarchical memory systems, making data movement often more critical than computation. Particular attention is given to issues such as aliasing, false sharing, and cache conflicts, which can significantly impact performance despite unchanged algorithms. The role of the compiler is emphasized as central in exploiting hardware capabilities, provided that code is well-structured and free from undefined behavior. Finally, the document underlines the limitations of general optimization rules and stresses the importance of empirical testing, as performance depends strongly on hardware characteristics and data layout.

An architecture of high performance computer,called Hyper Parallel Processing(HPP),is proposed to satisfy the requirements of both High Performance Computing,and Utility Computing which will be the application model of data centers.HPP combines the benefits of the scalability of MPP,the communication efficiency of DSM,as well as the commodity of cluster.Comparisons of current main-stream high performance computer architectures show that none of them can satisfy both HPC and utility computing.The main features of HPP are Global Address Space(GAS) and Hyper Node with single Operating System image.HPP supports the distributed global address space including both memory and I/O,but without hardware cache coherence.A Hyper Node consists of a set of application specific CPUs and a(or more) OS specific CPU.The OS CPU maintains the single system image,while the application CPUs run only lightweight run-time software.Besides the GAS interconnect network for applications,a standard SAN connects all OS CPUs and I/O devices providing system management and storage service.HPP is able to provide many opportunities of innovative research in High Performance and Utility Computing areas,including communication,synchronization,programming model,node operating system,utility computing,fault isolation,CPU and system etc.According to HPP architecture,a prototype system of Dawning5000 HPC is implemented and the feasibility of HPP is proved.

This work reports the detailed process of adapting an undergraduate discipline about High-Performance Computer Architecture, traditionally face-to-face taught, to be taught in a remote mode. The discipline is part of the curricula of two Computer Science undergraduate courses. The adaptation was carried out to comply with precaution measures to avoid the dissemination of the covid-19 disease, caused by the new coronavirus. The article describes the reorganizational and methodological processes to adapt a face-to-face discipline into a remote mode, discusses ways to implement the guidelines established by the Department of Computing and presents the new structure adopted for theoretical and practical classes, as well as the results of the assessment of the new teaching approach adopted for dealing with the pandemic. The process of adapting a face-to-face discipline to a remote mode was quite successful, considering the short period of time the adaptation needed to be implemented, as well as the many decisions involved in the processes detailed in the paper. The teaching-learning process throughout the remote course was considered satisfactory by the students, with a 95% confidence interval.

Transformations everywhere

At first thought, one may not realize the need for a special issue of Parallel and Distributed Computing Practices focused on Cluster Computing when our community has already invested years of research and spent a wealth of resources on traditional Big Iron supercomputers, for instance, the SGI/Cray Origin and IBM SP. Academia, industry, and national laboratories are still using, and for the foreseeable future, will continue to use, supercomputers to solve both grand-challenge scale and high-throughput applications. Then why the interest and new popularity of research into clusters for high-performance parallel and distributed applications? Clusters incorporate the tremendous successes that are attributable to our parallel and distributed processing community. Over the next decade, clusters will span the entire range of high-performance computing platforms. Instead of being restricted solely to supercomputers for achieving high-performance computing, the spectrum of available platforms will spread out to Beowulf-class clusters, to superclusters, and on to supercomputers. Moving along this continuum represents increasing computational resources, which in turn allows the capability for solving larger classes of applications or instances of problems. Compute-bound applications on workstations often may take advantage of the extra horsepower provided by symmetric multiprocessors. Applications with even larger computational requirements and a high-degree of concurrency may use Beowulf clusters, that is, clusters that are home-built from mass-market, commercial off-the-shelf workstations and networks, for instance, PC's interconnected by Fast Ethernet. A supercluster may contain commodity SMP nodes interconnected with scalable, low-latency, high-bandwidth networks, and is integrated by a system vendor rather than the computational scientist. Applications with greater complexity, for example, grand challenges from the sciences, demand scalable systems with high-performance, interconnects, perhaps coupled with terascale I/O subsystems, and thus, are appropriate for these superclusters. Finally, supercomputers, the largest of the clusters, may provide the ultimate platform for the highest-fidelity models and simulations and data-intensive applications. At each step up this ladder of cluster architectures, the system cost increases approximately by an order of magnitude, but having the high-performance capability to solve the problem of interest may require an entry point at any of these levels, the Beowulf, or supercluster, or even supercomputer platform. Cluster computing with Beowulf- or superclusters, thus, may be one or two orders of magnitude less expensive than a supercomputer, and provide a cost-effective solution and capability that was not available on a workstation. But this cost comparison measures just the basic system price. What about the applications? As recently as a few years ago, the lack of a canonical high-performance architectural paradigm meant that migrating to a new computer system, even from the same vendor, typically required redesigning applications to efficiently use the high-performance system. Thus, the application must be redesigned with parallel algorithms and libraries that are optimized for each high-performance system. This process of porting, redesigning, optimizing, debugging, and analyzing, the application may in fact be prohibitively expensive, and certainly frustrating when the process is completed just in time to greet the next generation system! That was then, this is now. With the successful standardization of system-level interfaces, many of these issues no longer hinder our expedited use of these new, high-performance clusters. The message-passing interface (MPI) is a clear example of a standard that has contributed significantly to the success of cluster computing. Supercomputer vendors working together with the high-performance computing community embarked on a process to standardize the user-level interface and behavior for passing messages between concurrent tasks. Now, using ordinary sequential compilers and vendor-supplied or freely-available implementations of this message-passing interface, applications can be implemented efficiently on one supercomputer and ported with little or no effort to other parallel machines. The message-passing paradigm, thus, provides a reasonably good canonical high-performance model and methodology for implementing high-performance applications. An algorithm that exhibits efficient execution and scaling on one machine then is likely to perform well on another with little or no additional programming effort. Using this cluster computing paradigm, algorithms typically are optimized by minimizing the number of remote memory accesses (reducing the amount of messages passed), and carefully organizing the data placement to increase memory locality. Thus, high-performance algorithms and applications that have been optimized for supercomputers, using the same cluster paradigm, may be appropriate for Beowulf and superclusters. Cluster computing, realizing the importance of a standard high-performance programming environment that applies equally well to both ends of the architectural spectrum, highly leverages these and other successes from parallel and distributed processing research and development. This is in an exciting, new era for high-performance computing where the canonical architectural paradigm stretches from home-built Beowulf clusters, to superclusters, and on to supercomputers. But cluster computing faces some challenges ahead of it. Continued research is required for designing 1) scalable, high-performance algorithms, applications, and methodologies, that can tolerate the communication overheads, and adapt to hybrid, SMP, and heterogeneous, nodes; 2) high-performance computer architectures, scalable interconnection networks, and I/O subsystems; and 3) scalable systems software, compilers, and monitoring tools. Cluster computing has come of age, and it is high time for the parallel and distributed processing community to lay the groundwork for our own legacy of success stories. David A. Bader University of New Mexico

The exponential growth in the amount of genomic data has spurred growing interest in large scale analysis of genetic information. Bioinformatics applications, which explore computational methods to allow researchers to sift through the massive biological data and extract useful information, are becoming increasingly important computer workloads. This paper presents BioPerf a benchmark suite of representative bioinformatics applications to facilitate the design and evaluation of high-performance computer architectures for these emerging workloads. Currently, the BioPerf suite contains codes from 10 highly popular bioinformatics packages and covers the major fields of study in computational biology such as sequence comparison, phylogenetic reconstruction, protein structure prediction, and sequence homology & gene finding. We demonstrate the use of BioPerf by providing simulation points of pre-compiled Alpha binaries and with a performance study on IBM Power using IBM Mambo simulations cross-compared with Apple G5 executions. The BioPerf suite (available from www.bioperf.org) includes benchmark source code, input datasets of various sizes, and information for compiling and using the benchmarks. Our benchmark suite includes parallel codes where available.

Modeling of containment structures on high performance computers

UNI–DEM is an Eulerian model for studying long range transport of air pollutants. The computational domain of the model covers Europe and some neighbour parts of Atlantic ocean, Asia and Africa. The model mainly is developed in the National Environmental Research Institute of Denmark, located at Roskilde. If UNI–DEM model is to be applied on a large space domain by using fine grids, then its discretization leads to a huge computational problem. If the space domain is discretized by using a (480 x 480) grid and the number of chemical species studied by the model is 35, then several systems of ordinary differential equations containing 8 064 000 equations have to be treated at every time-step (the number of time-steps being typically several thousand). If a three-dimensional version of the same air pollution model is to be used, then the figure above must be multiplied by the number of layers. This implies that such a model as UNI–DEM must be run only on high-performance computer architectures, like IBM Blue Gene/P. The implementatation of such complex large–scale model on each new computer is a non trivial task. Analysis of the runs of UNI–DEM performed until now on IBM Blue Gene/P computer is presented and some preliminary results on performance, speed ups and efficiency are discussed.

The paper focuses on the latest trends in supercomputer and high-performance computer architectures with emphasis of the important parameters for parallel computer performance. The main objective is to propose the high-speed network architecture for collective communications in supercomputers Silicon Galaxy that provides high-bandwidth, low latency and high tolerance to failures. The proposed network architecture Silicon Galaxy is composed of Milky Way Galaxy network for intercluster communication and Dwarf Galaxy network for communication within the cluster segments (intracluster communication in supercomputers). Communication performance of the proposed collective network has been evaluated on the base of parallel computer simulations on IBM Blade Center.

Loop optimization plays an important role in compiler optimization and program transformation. Many sophisticated techniques such as loop-invariance code motion have been developed. Loop peeling is a technique to assist parallelization of loops by unfolding loops a few times. This paper introduces a novel technique called loop peeling based on quasi-invariance/induction variables. It aims at finding a general and automatic method to derive how many times a given loop should be peeled. Our technique allows for a number of iterations before some variables assigned inside a given loop become invariance or induction variables. In this paper we define the notion of quasi-invariance/induction variables, present an algorithm for statically computing the optimal peeling length of a given loop. Our technique can increase the accuracy of program analyses, improve the effectiveness of loop peeling and is well-suited as supporting other optimization techniques in the context of supercomputers.

Compiler optimizations may break or weaken the security properties of a source program. This work develops a translation validation methodology for secure compilation. A security property is expressed as an automaton operating over a bundle of program traces. A refinement proof scheme derived from a property automaton guarantees that the associated security property is preserved by a program transformation. This generalizes known refinement methods that apply only to specific security properties. In practice, the refinement relations (“security witnesses”) are generated during compilation and validated independently with a refinement checker. This process is illustrated for common optimizations. Crucially, it is not necessary to formally verify the compiler implementation, which is infeasible for production compilers.

GriF is a Workflow Management System designed to support users of the Molecular and Materials Sciences and Technologies COMPCHEM Virtual Organization. In particular, GriF manages the results of the parameter sweeping studies submitted to the Grid. This service has been recently extended to implement seamless access to both High Performance and High Throughput Computing architectures. To this end, the Workflow execution is splitted into single blocks whose execution is most suited to one or the other platform. This has been obtained by implementing a communication channel allowing interoperability between the gLite middleware operating on the Italian Grid Initiative segment accessible to COMPCHEM and the software stack operating on the CINECA machines. As a prototype application a high level ab initio calculation of the potential energy surface of few atom system has been implemented.

Irregular memory access patterns pose performance and user productivity challenges on distributed-memory systems. They can lead to fine-grained remote communication and the data access patterns are often not known until runtime. The Partitioned Global Address Space (PGAS) programming model addresses these challenges by providing users with a view of a distributed-memory system that resembles a single shared address space. However, this view often leads programmers to write code that causes fine-grained remote communication, which can result in poor performance. Prior work has shown that the performance of irregular applications written in Chapel, a high-level PGAS language, can be improved by manually applying optimizations. However, applying such optimizations by hand reduces the productivity advantages provided by Chapel and the PGAS model. We present an inspector-executor based compiler optimization for Chapel programs that automatically performs remote data replication. While there have been similar compiler optimizations implemented for other PGAS languages, high-level features in Chapel such as implicit processor affinity lead to new challenges for compiler optimization. We evaluate the performance of our optimization across two irregular applications. Our results show that the total runtime can be improved by as much as 52x on a Cray XC system with a low-latency interconnect and 364x on a standard Linux cluster with an Infiniband interconnect, demonstrating that significant performance gains can be achieved without sacrificing user productivity.

Execution environments are used as specifications for specialization of input-output programs in the derivation of product lines. These environments, formalized as color-blind I/O-alternating transition systems, are tolerant to mutations in a given program's outputs. Execution environments enable new compiler optimizations, vastly exceeding usual reductions. We propose a notion of context-dependent refinement for I/O-alternating transition systems, which supports composition and hierarchical reuse. The framework is demonstrated by discussing adaptations to realistic design languages and by presenting an exampleof a product line.