"Silicon Galaxy" system area network for collective communication in supercomputers

The need for large scale parallel computer systems has been intensified by the number of applications which require manipulation of large amount of data. Many scientific and engineering applications require high performance parallel computers to accomplish the computational tasks. This paper presents a multiple bus architecture capable of being scaled to massive dimension, to handle large amounts of data. The memory bandwidth of this architecture is analyzed. This architecture has low latency and high bus bandwidth. Also the architecture can enforce cache consistency through bus snooping cache coherence protocols.

A 3D Free Surface Flow and Transport Model on Different High Performance Computation Architectures

The Study on the Communication Network of Wide Area Measurement System in Electricity Grid

Wide Area Measurement Systems (WAMS) use an underlying communication network to collect and analyze data from devices in the power grid, aimed to improve grid operations. For WAMS to be effective, the communication network needs to support low packet latency and low packet losses. Internet Protocol (IP), the pervasive technology used in today's communication networks uses loop-free best-paths for data forwarding, which increases the load on these paths causing delays and losses in delivery. Information-Centric Networking (ICN), a new networking paradigm, designed to enable a data-centric information sharing, natively supports the concurrent use of multiple transmission interfaces, in-networking caching, as well as per-packet security and can provide better application support. In this paper, we present iCASM, an ICN-based network architecture for wide area smart grid communications. We demonstrate through simulations that iCASM achieves low latency and 100% data delivery even during network congestion by leveraging multiple available paths; thus significantly improving communication resiliency in comparison to an IP-based approach. iCASM can be used immediately on today's Internet as an overlay.

A critical piece of the Smart Grid (SG) infrastructure is the supporting Communication Networks that facilitate data gathering, monitoring and control of the electric grid. Over the years, electric utilities built robust communication networks for their transmission and distribution systems, but stopped short of the "last mile" connections to the end user. A primary goal of the SG is to expand the communications network throughout and beyond the Distribution Network (DN); thus, enabling a holistic management and control of the electric grid from generation to consumption. For the realization of the Smart Grid goals, two-way communication capabilities must extend beyond the Distribution Network to the end user, allowing two-way data flow, e.g., real-time energy pricing as well as real-time demand data back to the utility operators. Selecting an appropriate communications architecture is the first and most important decision in designing a communications network since it will have lasting effects on the efficiency, reliability and cost of the network. This paper presents and evaluates various communication architectures for deployment of the SG within the DN and to the end users.

With the rapid development of mobile communication technology, wireless services and application scenarios are evolving toward diversification and intelligence. Large bandwidth, low latency, and massive connections are urgent needs for future network development, and traditional communication network architectures can no longer adapt. With the development of contemporary communication networks, the network architecture of C-RAN (Centralized, Cooperative, Cloud Radio Access Network) can concentrate base station processing resources, dynamically allocate transmitted signals, and have high spectrum utilization. In signal transmission, it also has the advantages of high efficiency, flexible scheduling and energy saving. However, the limited capacity of the fronthaul link under the C-RAN architecture makes signal compression and decompression especially important. This paper proposes an efficient and stable compressed sensing algorithm-a new stepwise orthogonal matching pursuit algorithm (NStOMP algorithm). First, the algorithm does not depend on the number of atoms selected in each iteration, S, and achieves stable compressed signal transmission. Secondly, it combines the idea of backtracking to filter the wrongly selected atoms in the first screening, and performs the second screening of atoms to reconstruct and restore the signal with a higher probability. This paper compares the proposed NStOMP algorithm with the improved StOMP algorithm and other common CS algorithms. The simulation results verify the stability of the proposed algorithm and its advantages compared with the reconstruction effect of common signal compression algorithms. It has better application value in the actual fronthaul network architecture.

A survey on the communication architectures in smart grid

This paper presents Lotterybus, a novel high-performance communication architecture for system-on-chip (SoC) designs. The Lotterybus architecture was designed to address the following limitations of current communication architectures: (i) lack of control over the allocation of communication bandwidth to different system components or data flows (e.g., in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the communication requests (e.g., in time division multiplexed access (TDMA) based architectures), sometimes leading to larger latencies for high-priority communications.We present two variations of Lotterybus: the first is a low overhead architecture with statically configured parameters, while the second variant is a more sophisticated architecture, in which values of the architectural parameters are allowed to vary dynamically.Our experiments investigate the performance of the Lotterybus architecture across a wide range of communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the Lotterybus architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority communication traffic with low latencies (we observed upto 85.4\% reduction in communication latencies over conventional on-chip communication architectures).

The Industrial Internet of things (IIoT), the implementation of IoT in the industrial sector, requires a deterministic, real-time, and low-latency communication response for its time-critical applications. A delayed response in such applications could be life-threatening or result in significant losses for manufacturing plants. Although several measures in the likes of predictive maintenance are being put in place to prevent errors and guarantee high network availability, unforeseen failures of physical components are almost inevitable. Our research contribution is to design an efficient communication prototype, entirely based on internet protocol (IP) that combines state-of-the-art communication computing technologies principles to deliver a more stable industrial communication network. We use time-sensitive networking (TSN) and edge computing to increase the determinism of IIoT networks, and we reduce latency with zero-loss redundancy protocols that ensure the sustainability of IIoT networks with smooth recovery in case of unplanned outages. Combining these technologies altogether brings more effectiveness to communication networks than implementing standalone systems. Our study results develop two experimental IP-based industrial network communication prototypes in an intra-domain transmission scenario: the first one is based on the parallel zero-loss redundancy protocol (PRP) and the second one using the high-availability seamless zero-loss redundancy protocol (HSR). We also highlight the benefits of utilizing our communication prototypes to build robust industrial IP communication networks with high network availability and low latency as opposed to conventional communication networks running on seldom redundancy protocols such as Media Redundancy Protocol (MRP) or Rapid Spanning Tree Protocol (RSTP) with single-point of failure and delayed recovery time. While our two network communication prototypes—HSR and PRP—offer zero-loss recovery time in case of a single network failure, our PRP communication prototype goes a step further by providing an effective redundancy scheme against multiple link failures.

This work reports the detailed process of adapting an undergraduate discipline about High-Performance Computer Architecture, traditionally face-to-face taught, to be taught in a remote mode. The discipline is part of the curricula of two Computer Science undergraduate courses. The adaptation was carried out to comply with precaution measures to avoid the dissemination of the covid-19 disease, caused by the new coronavirus. The article describes the reorganizational and methodological processes to adapt a face-to-face discipline into a remote mode, discusses ways to implement the guidelines established by the Department of Computing and presents the new structure adopted for theoretical and practical classes, as well as the results of the assessment of the new teaching approach adopted for dealing with the pandemic. The process of adapting a face-to-face discipline to a remote mode was quite successful, considering the short period of time the adaptation needed to be implemented, as well as the many decisions involved in the processes detailed in the paper. The teaching-learning process throughout the remote course was considered satisfactory by the students, with a 95% confidence interval.

At first thought, one may not realize the need for a special issue of Parallel and Distributed Computing Practices focused on Cluster Computing when our community has already invested years of research and spent a wealth of resources on traditional Big Iron supercomputers, for instance, the SGI/Cray Origin and IBM SP. Academia, industry, and national laboratories are still using, and for the foreseeable future, will continue to use, supercomputers to solve both grand-challenge scale and high-throughput applications. Then why the interest and new popularity of research into clusters for high-performance parallel and distributed applications? Clusters incorporate the tremendous successes that are attributable to our parallel and distributed processing community. Over the next decade, clusters will span the entire range of high-performance computing platforms. Instead of being restricted solely to supercomputers for achieving high-performance computing, the spectrum of available platforms will spread out to Beowulf-class clusters, to superclusters, and on to supercomputers. Moving along this continuum represents increasing computational resources, which in turn allows the capability for solving larger classes of applications or instances of problems. Compute-bound applications on workstations often may take advantage of the extra horsepower provided by symmetric multiprocessors. Applications with even larger computational requirements and a high-degree of concurrency may use Beowulf clusters, that is, clusters that are home-built from mass-market, commercial off-the-shelf workstations and networks, for instance, PC's interconnected by Fast Ethernet. A supercluster may contain commodity SMP nodes interconnected with scalable, low-latency, high-bandwidth networks, and is integrated by a system vendor rather than the computational scientist. Applications with greater complexity, for example, grand challenges from the sciences, demand scalable systems with high-performance, interconnects, perhaps coupled with terascale I/O subsystems, and thus, are appropriate for these superclusters. Finally, supercomputers, the largest of the clusters, may provide the ultimate platform for the highest-fidelity models and simulations and data-intensive applications. At each step up this ladder of cluster architectures, the system cost increases approximately by an order of magnitude, but having the high-performance capability to solve the problem of interest may require an entry point at any of these levels, the Beowulf, or supercluster, or even supercomputer platform. Cluster computing with Beowulf- or superclusters, thus, may be one or two orders of magnitude less expensive than a supercomputer, and provide a cost-effective solution and capability that was not available on a workstation. But this cost comparison measures just the basic system price. What about the applications? As recently as a few years ago, the lack of a canonical high-performance architectural paradigm meant that migrating to a new computer system, even from the same vendor, typically required redesigning applications to efficiently use the high-performance system. Thus, the application must be redesigned with parallel algorithms and libraries that are optimized for each high-performance system. This process of porting, redesigning, optimizing, debugging, and analyzing, the application may in fact be prohibitively expensive, and certainly frustrating when the process is completed just in time to greet the next generation system! That was then, this is now. With the successful standardization of system-level interfaces, many of these issues no longer hinder our expedited use of these new, high-performance clusters. The message-passing interface (MPI) is a clear example of a standard that has contributed significantly to the success of cluster computing. Supercomputer vendors working together with the high-performance computing community embarked on a process to standardize the user-level interface and behavior for passing messages between concurrent tasks. Now, using ordinary sequential compilers and vendor-supplied or freely-available implementations of this message-passing interface, applications can be implemented efficiently on one supercomputer and ported with little or no effort to other parallel machines. The message-passing paradigm, thus, provides a reasonably good canonical high-performance model and methodology for implementing high-performance applications. An algorithm that exhibits efficient execution and scaling on one machine then is likely to perform well on another with little or no additional programming effort. Using this cluster computing paradigm, algorithms typically are optimized by minimizing the number of remote memory accesses (reducing the amount of messages passed), and carefully organizing the data placement to increase memory locality. Thus, high-performance algorithms and applications that have been optimized for supercomputers, using the same cluster paradigm, may be appropriate for Beowulf and superclusters. Cluster computing, realizing the importance of a standard high-performance programming environment that applies equally well to both ends of the architectural spectrum, highly leverages these and other successes from parallel and distributed processing research and development. This is in an exciting, new era for high-performance computing where the canonical architectural paradigm stretches from home-built Beowulf clusters, to superclusters, and on to supercomputers. But cluster computing faces some challenges ahead of it. Continued research is required for designing 1) scalable, high-performance algorithms, applications, and methodologies, that can tolerate the communication overheads, and adapt to hybrid, SMP, and heterogeneous, nodes; 2) high-performance computer architectures, scalable interconnection networks, and I/O subsystems; and 3) scalable systems software, compilers, and monitoring tools. Cluster computing has come of age, and it is high time for the parallel and distributed processing community to lay the groundwork for our own legacy of success stories. David A. Bader University of New Mexico

Analyzing and optimizing program memory performance is a pressing problem in high-performance computer architectures. Currently, software solutions addressing the processor-memory performance gap include compiler-or programmer-applied optimizations like data structure padding, matrix blocking, and other program transformations. Compiler optimization can be effective, but the lack of precise analysis and optimization frameworks makes it impossible to confidently make optimal, rather than heuristic-based, program transformations. Imprecision is most problematic in situations where hard-to-predict cache conflicts foil heuristic approaches. Furthermore, the lack of a general framework for compiler memory performance analysis makes it impossible to understand the combined effects of several program transformations.The Cache Miss Equation (CME) framework discussed in this paper addresses these issues. We express memory reference and cache conflict behavior in terms of sets of equations. The mathematical precision of CMEs allows us to find true optimal solutions for transformations like blocking or padding. The generality of CMEs also allows us to reason about interactions between transformations applied in concert. Unlike our prior work, this framework applies to caches of arbitrary associativity. This paper also demonstrates the utility of CMEs by presenting precise algorithms for intra-variable padding, inter-variable padding, and selecting tile sizes. Our experiences with CMEs implemented in the SUIF system show that they are a unifying mathematical framework offering the generality and precision imperative for compiler optimizations on current high-performance architectures.

An architecture of high performance computer,called Hyper Parallel Processing(HPP),is proposed to satisfy the requirements of both High Performance Computing,and Utility Computing which will be the application model of data centers.HPP combines the benefits of the scalability of MPP,the communication efficiency of DSM,as well as the commodity of cluster.Comparisons of current main-stream high performance computer architectures show that none of them can satisfy both HPC and utility computing.The main features of HPP are Global Address Space(GAS) and Hyper Node with single Operating System image.HPP supports the distributed global address space including both memory and I/O,but without hardware cache coherence.A Hyper Node consists of a set of application specific CPUs and a(or more) OS specific CPU.The OS CPU maintains the single system image,while the application CPUs run only lightweight run-time software.Besides the GAS interconnect network for applications,a standard SAN connects all OS CPUs and I/O devices providing system management and storage service.HPP is able to provide many opportunities of innovative research in High Performance and Utility Computing areas,including communication,synchronization,programming model,node operating system,utility computing,fault isolation,CPU and system etc.According to HPP architecture,a prototype system of Dawning5000 HPC is implemented and the feasibility of HPP is proved.

The future intelligent network requires seamless coverage, low latency, and ultrareliable communication, which is far from enough for the current vehicular network. The space–air–ground integrated network (SAGIN) includes the ground, air, and space network segments, which is considered a new network architecture for future intelligent communications. Then, we introduce a novel network architecture that uses SAGIN to assist the vehicular network to form a space–air–ground integrated vehicular network (SAGIVN). By using a SAGIN assist vehicular network, the vehicular network can obtain unprecedented performance. However, due to the highly heterogeneous and dynamic characteristics of SAGIVN, the management of resource pools and the conversion of communication among heterogeneous nodes are considerable challenges. As a powerful artificial intelligence tool, machine learning plays a vital role in wireless networks. In this article, we introduce several applications of machine learning technology in SAGIVN. In order to better illustrate the feasibility of the application of machine learning in SAGIVN, we further propose a case study of a traffic offloading scheme based on federated reinforcement learning in SAGIVN.

The meaning of a place has been commonly assigned to the quality of having root (rootedness) or sense of belonging to that setting. While on the contrary, people are nowadays more concerned with the possibilities of free moving and networks of communication. So, the meaning, as well as the materiality of architecture has been dramatically altered with these forces. It is therefore of significance to explore and redefine the sense and the trend of architecture at the age of flow. In this dissertation, initially, we review the gradually changing concept of and its underlying technological basis. Then we portray the transformation of meaning of architecture as influenced by media and information technology and advanced methods of mobility, in the dawn of 21st century. Against such backdrop, there is a need to sort and analyze architectural practices in response to the triplet of place-non-place and space of flow, which we plan to achieve conclusively. We also trace the concept of in the process of formation and transformation of old cities. As a brilliant case study, we look at Persian Bazaar from a socio-architectural point of view. In other word, based on Robert Putnam's theory of social capital, we link social context of the Bazaar with architectural configuration of cities. That is how we believe cities as flow are not necessarily a new paradigm.