PRIORITY-DRIVEN AREA OPTIMIZATION IN HIGH-LEVEL SYNTHESIS

Background: In recent years, the rising demand for high-performance radar systems in aeronautics, astronautics, national defense, and civil communication has driven the widespread application of phased-array technology. The design of beam controllers, the core of phased-array systems, faces many challenges. Traditional implementation schemes are usually based on application-specific integrated circuits (ASIC) or discrete components, which have a long development cycle, poor flexibility, and limited adaptability. Field-programmable gate arrays (FPGA), with their high parallelism, reconfigurability, and powerful signal processing capabilities, offer a new way to implement phased-array control systems. But FPGA design has traditionally relied on register transfer level (RTL) description, which is inefficient and struggles to keep up with the rapid iteration of complex algorithms. With the development of high-level synthesis (HLS) technology, it has become possible to develop FPGAs using high-level languages such as C/C++. However, improving development efficiency while ensuring hardware performance remains a key issue in the design of phased-array beam controllers. Materials and Methods: This study employs an HLS - RTL co - design method to build a phased - array beam controller. This approach combines the strengths of HLS's efficient algorithm implementation and RTL's precise hardware interface control. The system architecture consists of three parts: the host - machine control layer, FPGA processing layer, and phase - control output layer. In the FPGA processing layer, the core beam - forming algorithm is implemented via HLS. Based on phased - array principles, this algorithm converts target angles to wave vectors and calculates phase - compensation values for each element in an 8×8 array. Pipelining and parallel processing techniques are used in the HLS design to optimize algorithm throughput and latency. The phase - control output layer, designed with RTL, repackages 64 calculated phase values and distributes them to 16 physical phase - shifter chips. Each phase - shifter manages four elements and receives control data through an SPI interface. Results: The proposed FPGA-based phased-array beam controller design in this paper has successfully achieved high - speed, high - precision beam control. By using the HLS - RTL co - design method, it has solved the problem of low algorithm implementation efficiency in traditional FPGA development and ensured the high performance and reliability of hardware interfaces. Experimental results indicate that the system meets or surpasses design targets on key performance indicators. Its end - to - end latency is kept within 130μs, it supports an angle update rate of over 5,000 times per second, and can satisfy the requirements for tracking highly dynamic targets in practical applications. Conclusion: The major contributions of this research are as follows: presenting an HLS - RTL co - design methodology for complex FPGA system development; designing an efficient phased - array beam - forming algorithm and its hardware implementation; and developing a flexible and scalable phased - array control system architecture that supports different array configurations. These findings are highly significant for beamforming technologies in phased - array radar and 5G communication systems, as well as for other FPGA applications requiring high - speed signal processing.

Reducing resource usage is one of the most important optimization objectives in behavioral synthesis due to its direct impact on power, performance and cost. The datapath in a typical design is composed of different kinds of components, including functional units, registers and multiplexers. To optimize the overall resource usage, a behavioral synthesis tool should consider all kinds of components at the same time. However, most previous work on behavioral synthesis has the limitations of (i) not being able to consider all kinds of resources globally, and/or (ii) separating the synthesis process into a sequence of optimization steps without a consistent optimization objective. In this paper we present a behavioral synthesis flow in which all types of components in the datapath are modeled and optimized consistently. The key idea is to feed to the scheduler the intentions for sharing functional units and registers in favor of the global optimization goal (such as total area), so that the scheduler could generate a schedule that makes the sharing intentions feasible. Experiments show that compared to the solution of minimizing functional unit requirements in scheduling and using the least number of functional units and registers in binding, our solution achieves a 24% reduction in total area; compared to the online tool provided by c-to-verilog.com, our solution achieves a 30% reduction on average.

Current trends in computing require dedicated chips to speed up computing performances. These dedicated chips or ASICs are designed for specific applications, however, the drawback in this approach is that IC (Integrated Circuits) functionality cannot be changed. In areas where H/W programmability and reconfigurability is required, FPGA is the solution to achieve this. System on Chip (SOC) FPGAs (Field Programmable Gate Arrays) include processor hard blocks connected to fabric through various interconnects. This architecture provides better performance and the ability to run Operating Systems (OS) like Linux <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> that has direct access to programmable FPGA logic. This paper explains how to split the functions of an application code between hard block processor and FPGA fabric logic. OPUS is an open-source audio codec widely used in voice-over-IP (VoiP) applications. The codec execution can be accelerated by moving some of its functions to FPGA logic. One such function of OPUS code is implemented in FPGA logic using High-Level Synthesis (HLS). Shared DDR memory space is used to transfer the data between the processor and FPGA. In this paper, we summarize the reduction in execution time and processor load. The acceleration of OPUS codec allows processing of a greater number of audio channels in the SoC device compared to running the codec entirely on the processor.

The use of abstract data types for high-level synthesis is addressed. It is demonstrated how data types can be used in the synthesis process to achieve reductions in area and delay of the logic level implementation. Four fundamental type constructs-structures, unions, vectors, and enumerations-are considered. Data types and functions on their values are extended to support don't care information. Supporting abstract data types in behavioral representations is addressed for both an internal data-flow representation and the ELLA hardware description language. Finally, synthesis results for several design examples are presented. Smaller and faster implementations are obtained by supporting encoding and don't care minimization in the high-level synthesis process. >

This paper explores real-time Convolutional Neural Network inference on Field Pro- grammable Gate Arrays (FPGAs) implemented in Synchronous Message Exchange (SME). We compare SME to the widespread FPGA tool, High-Level Synthesis (HLS), and com- pare both the SME and HLS implementations of CNNs with the PyTorch implementation for CNN on CPU/GPU. We find that the SME implementation is more flexible than the HLS implementation as it allows for more customization of the hardware. Programming with SME is more difficult than HLS, although easier than traditional Hardware Descrip- tion Languages. Finally, for a test use case, we find that the SME implementation on FPGA is approximately 2.8/1.4/2.0 times more energy efficient than CPU/GPU/ARM at larger batch sizes, with the HLS implementation on FPGA falling in between CPU/ARM and GPU in terms of energy efficiency. At a batch size of 1, appropriate for edge-device inference, the gap in energy efficiency between the FPGA and CPU/GPU/ARM imple- mentations becomes more pronounced, with the SME implementation on FPGA being approximately 83/47/8 times more energy efficient than the CPU/GPU/ARM implemen- tations, and with the HLS implementation on FPGA being approximately 40/23/4 times more energy efficient than the CPU/GPU/ARM implementations.

The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes as input an untimed behavioral description and generates efficient RTL (Verilog or VHDL). One major advantage of HLS is that it allows us to generate a variety of different micro-architectures from the same behavioral description by simply specifying different combination of synthesis options. In particular, commercial HLS tools make extensive use of synthesize directives in the form pragmas. This strength is also a weakness as it forces HLS users to fully understand how these synthesis options work and how they interact to efficiently set them to get a hardware implementation with the desired characteristics. Luckily, this process can be automated. Unfortunately, the search space grows supra-linearly with the number of synthesis options. To address this, this work proposes an automatic synthesis option tuner dedicated for FPGAs. We have explored a larger number of behavioral descriptions targeting ASICs and FPGAs and found out that due to the internal structure of the FPGA a large number of synthesis options combinations never lead to a Pareto-optimal design and, hence, the search space can be drastically reduced. Moreover, we make use of large database of DSE results that we have generated since we started working in this field to further accelerate the exploration process. For this, we use a technique based on perceptual hashing that allows our proposed explorer to recognize similar program structures in the new description to be explored and match them with structures in our database. This allows us to directly retrieve the pragma settings that lead to Pareto-optimal configurations. Experimental results show that the search space can be accelerated substantially while leading to finding most of the Pareto-optimal designs.

Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.KeywordsHigh-level synthesis (HLS)Neural networks (NNs)Register transfer level (RTL)Field-programmable gate arrays (FPGAs)Systems on chip (SOC)Artificial intelligence (AI)Graphic processing units (GPUs)Generalized NNs (GNN)Recurrent neural network (RNN)Feed-forward neural networks (FFNNs)

The escalating demand for data processing in particle physics research has spurred the exploration of novel technologies to enhance the efficiency and speed of calculations. This study presents the development of an implementation of MADGRAPH, a widely used tool in particle collision simulations, to Field Programmable Gate Array (FPGA) using High-Level Synthesis (HLS). This research presents a proof of concept limited to a single, relatively simple process e+e−→μ+μ−. The experimental evaluation methodology is described, focusing on performance comparison between traditional CPU implementations, GPU acceleration, and the new FPGA approach. This study describes the complex process of adapting MADGRAPH to FPGA using HLS, focusing on optimizing algorithms for parallel processing. These advancements could enable faster execution of complex simulations, highlighting FPGA’s crucial role in advancing particle physics research. The encouraging results obtained in this proof of concept prove potential interest in testing the performance of the FPGA implementation of more complex processes.

Field Programmable Gate Arrays (FPGAs) have been targeted as a new accelerator of the HPC field. This is because the barrier to using FPGAs has been gradually lowered due to the widespread use of high-level synthesis (HLS) technology. In addition, the bandwidth of external memory in FPGAs is much lower than that of other accelerators widely used in HPC, such as NVIDIA V100 GPUs. However, the latest FPGAs can use High Bandwidth Memory 2 (HBM2), which has a memory bandwidth of up to 512GB/s. Therefore, we believe FPGAs will be a viable option for speeding up applications. However, unlike CPUs and GPUs, FPGAs do not have caches and memory networks to exploit the full potential of HBM2, which may limit the efficiency of the application. In this paper, we propose a memory system for HBM2 and HPC applications. We show the prototype implementation of the system and evaluate its performance. We also demonstrate the use of the proposed system from an application developed in High-Level Synthesis (HLS) written in C++.

Over the course of 60 years, since the invention of the integrated circuit (IC), exponential improvements in cost, performance and power consumption were observed. Such advances have been strongly linked with the continuous reduction of the dimensions in manufactured ICs, but this trend has shown decreasing benefits as fundamental limits are reached. Notice that such tiny devices have increased variability, which generates unpredictable variations in the behavior of the manufactured devices. These uncertainties are typically addressed by defining margins on the clock period, estimated during the design phase. However, the overly conservative margins produce significant degradations in performance. Additionally, the evolution that enabled circuits with increasingly higher density of components, also resulted in an extremely complex IC design. At every step, electronic design automation (EDA) tools are challenged to handle this increasing complexity, requiring more powerful techniques to comply with the specification constraints within an affordable runtime. This thesis investigates alternatives in order to improve power, performance, area, and cost, using established IC manufacturing technologies. Advances in EDA are proposed in three distinct topics: area minimization using Boolean methods, area and delay reduction for designs based on fieldprogrammable gate array (FPGA), and an alternative clocking scheme to reduce timing margins. The first contribution consists of a technology-independent method for area minimization of combinational logic. Local optimization is applied on and-inverter graphs (AIGs), performing multi-output Boolean decomposition using two-literal divisors, targeting node count reduction. The second contribution regards two methods targeting technology mapping of FPGAs. On one hand, a functional decomposition approach, which uses the support size as cost function, exploring the inherent characteristics of FPGAs. On the other hand, an approach for recursive remapping, which reduces the structural bias of the subject graph, uses the mapping results as cost function, and obtains significant reductions in area and delay. The third contribution evaluates the dynamic variability mitigation and simplification of power delivery networks (PDNs) using an adaptive clocking scheme based on ring oscillator clocks (ROCs). The impact of the PDN parameters and ROC location is investigated, showing potential improvements in performance, leakage power and cost. A lo largo de los 60 años desde la invención del circuito integrado (CI), se han producido mejoras exponenciales en su coste, rendimiento y consumo de energía. Ese progreso esta fuertemente vinculado a la reducción continua de las dimensiones de fabricación de los circuitos integrados, pero esta tendencia ha ido mostrando menos beneficios a medida que se alcanzan límites fundamentales. Estos dispositivos minúsculos tienen una mayor variabilidad, lo que genera variaciones impredecibles en el comportamiento de los dispositivos fabricados. Estas incertidumbres generalmente se abordan mediante la definición de márgenes en el período de reloj, estimado durante la fase de diseño. Sin embargo, márgenes excesivamente conservadores producen degradaciones significativas en el rendimiento. Además, la evolución que permitió crear circuitos con una densidad de componentes cada vez mayor, también incrementado la complejidad de los CI. En cada paso del proceso de diseño, las herramientas de automatización de diseño electrónico (EDA) se enfrentan al desafío de manejar esta complejidad creciente, lo que requiere técnicas más potentes para cumplir con las restricciones impuestas por las especificaciónes dentro de un tiempo de ejecución asequible. Esta tesis investiga alternativas para mejorar el consumo de energía, el rendimiento, el área y el coste, utilizando las tecnologías de fabricación de CI ya establecidas. Los avances en EDA se proponen en tres temas distintos: minimización de área usando métodos booleanos, reducción de retardo y área para diseños basados en matrices de puertas programables (FPGA), y un esquema de reloj alternativo para reducir los márgenes de tiempo excesivamente conservadores. La primera contribución consiste en un método independiente de tecnología para minimizar el área de la lógica combinacional. Se aplica optimización local en grafos de AND-inversor, utilizando una descomposición Booleana de múltiples salidas con divisores de dos literales, con el objetivo de reducir la cantidad de nodos. La segunda contribución propone dos métodos para el mapeo tecnológico de los FPGA. Por un lado, un método de descomposición funcional, que utiliza el tamaño del soporte como función de coste, explorando las características inherentes de los FPGA. Por otro lado, un método de mapeo recursivo, que reduce la distorsión estructural del grafo sujeto, utiliza los resultados del mapeo como función de coste y obtiene reducciones significativas en área y retardo. La tercera contribución evalúa la mitigación de la variabilidad dinámica y la simplificación de la red de suministro de energía (PDN) utilizando un esquema de reloj adaptativo basado en un oscilador en anillo (ROC). Se investiga el impacto de los parámetros de la PDN y la ubicación del ROC, mostrando mejoras potenciales en el rendimiento, consumo estático y coste.

Field Programmable Gate Arrays (FPGAs) play a significant role in computationally intensive network processing due to their flexibility and efficiency. Particularly with the high-level abstraction of the P4 network programming model, FPGA shows a powerful potential for packet processing. By supporting the P4 language with FPGA processing, network researchers can create customized FPGA-based network functions and execute network tasks on accelerators directly connected to the network. A feature of the P4 language is that it is stateless; however, the FPGA implementation in this research requires state information. This is accomplished using P4 externs to describe the stateful portions of the design and to implement them on the FPGA using High-Level Synthesis (HLS). This paper demonstrates using an FPGA-based SmartNIC to efficiently extract source-destination IP address information from network packets and construct anonymized network traffic matrices for further analysis. The implementation is the first example of the combination of using P4 and HLS in developing network functions on the latest AMD FPGAs. Our design achieves a processing rate of approximately 95 Gbps with the combined use of P4 and High-level Synthesis and is able to keep up with 100 Gbps traffic received directly from the network.

This paper presents a novel approach to optimize the performance of a design synthesized from a given behavioral application. The high-level synthesis process is highly restricted by a pre-characterized library from which components are chosen to implement operations in the behavior. Moreover logic optimization on the register-transfer level datapath is typically limited to within the register boundaries that enclose the chosen components. It is imperative that the datapath components be carefully selected and synthesized in order to obtain a performance gain. The technique presented in this paper consists of two primary steps, application-specific macro generation and replacement, that are performed prior to high-level synthesis, The macro generation step extracts macro subgraphs from the given application graph and generates a macro component (an equivalent netlist)for each macro subgraph. Further; each macro component is optimized for performance using commercial logic synthesis tools. Using the enriched component library, a macro replacement step modifies the behavioral graph such that some subgraphs are replaced by equivalent macros. The replacement step attempts to replace subgraphs such that the design latency is minimized. The modified behavioral graph along with the enriched component library is then taken through high-level, logic and layout synthesis. Experiments on DSP benchmarks show that the macro based synthesis process achieves significant improvement in design performance as opposed to the traditional design process. We have developed an automated performance-optimization framework that is only limited by the optimization capability of backend tools.

FPGAs (Field-Programmable Gate Array) may offer higher performance than CPU architectures. Hardware Description Languages (HDL), such as VHDL and Verilog, which are traditionally used to program FPGAs, are known as hard to learn, to use, and to debug. Optionally, High Level Synthesis (HLS), such as OpenCL, allows developers to focus on the design of functions following a high-level software development flow, makes it easier to program FPGAs. This paper implements an image filter in the frequency domain on an FPGA board by using OpenCL, making the FPGA board an accelerator device to the host PC. The experiment results show that the filter implemented on the FPGA device can be optimized by pipelining the signal processing tasks onto the FPGA and reduce the I/O requirements between host PC and FPGA. The optimized FPGA implementation has higher performance than the image filter totally implemented on CPU.

Being lossless, Reversible Image Watermarking (RIW) with Difference Expansion (DE) algorithm is crucial for content authentication, especially for high security medical and military images. In DE-RIW, the secret data bit can be embedded into the Least Significant Bit (LSB) of the difference between two neighboring pixels. Very few researchers have worked on High Level Synthesis (HLS) based implementation of its modified algorithm on Field Programmable Gate Array (FPGA) and Programmable System-On-Chip (P-SoC). Here, to get accelerated performance a modified DE-RIW algorithm is proposed along with its VLSI based hardware implementation both on Xilinx FPGA and P-SoC. In the proposed approach, scheduling is done considering resource constraint criteria. Implementation results through simulation up to burning the design on board needs fewer resources (adder, subtractor, multiplier, divider, register, multiplexer, and comparator) as compared with the similar existing architectures in the literature based on RIW.

Field Programmable Gate Arrays (FPGAs) have been indispensable components of embedded systems and datacenter infrastructures. However, energy efficiency of FPGAs has become a hard barrier preventing their expansion to more application contexts, due to two physical limitations: (1) The massive usage of routing multiplexers causes delay and power overheads as compared to ASICs. To reduce their power consumption, FPGAs have to operate at low supply voltage but sacrifice performance because the transistors drive degrade when working voltage decreases. (2) Using volatile memory technology forces FPGAs to lose configurations when powered off and to be reconfigured at each power Resistive Random Access Memories (RRAMs) have strong potentials in overcoming the physical limitations of conventional FPGAs. First of all, RRAMs grant FPGAs non-volatility, enabling FPGAs to be Normally powered off, Instantly powered on. Second, by combining functionality of memory and pass-gate logic in one unique device, RRAMs can greatly reduce area and delay of routing elements. Third, when RRAMs are embedded into datpaths, the performance of circuits can be independent from their working voltage, beyond the limitations of CMOS circuits. However, researches and development of RRAM-based FPGAs are in their infancy. Most of area and performance predictions were achieved without solid circuit-level simulations and sophisticated Computer Aided Design (CAD) tools, causing the predicted improvements to be less convincing. In this thesis,we present high-performance and low-power RRAM-based FPGAs fromtransistorlevel circuit designs to architecture-level optimizations and CAD tools, using theoretical analysis, industrial electrical simulators and novel CAD tools. We believe that this is the first systematic study in the field, covering: From a circuit design perspective, we propose efficient RRAM-based programming circuits and routing multiplexers through both theoretical analysis and electrical simulations. The proposed 4T(ransitor)1R(RAM) programming structure demonstrates significant improvements in programming current, when compared to most popular 2T1R programming structure. 4T1R-based routingmultiplexer designs are proposed by considering various physical design parasitics, such as intrinsic capacitance of RRAMs and wells doping organization. The proposed 4T1R-based multiplexers outperformbest CMOS implementations significantly in area, delay and power at both nominal and near-Vt regime. From a CAD perspective, we develop a generic FPGA architecture exploration tool, FPGASPICE, modeling a full FPGA fabric with SPICE and Verilog netlists. FPGA-SPICE provides different levels of testbenches and techniques to split large SPICE netlists, in order to obtain better trade-off between simulation time and accuracy. FPGA-SPICE can capture area and power characteristics of SRAM-based and RRAM-based FPGAs more accurately than the currently best analyticalmodels. From an architecture perspective, we propose architecture-level optimizations for RRAMbased FPGAs and quantify their minimumrequirements for RRAM devices. Compared to the best SRAM-based FPGAs, an optimized RRAM-based FPGA architecture brings significant reduction in area, delay and power respectively. In particular, RRAM-based FPGAs operating in the near-Vt regime demonstrate a 5x power improvement without delay overhead as compared to optimized SRAM-based FPGA operating at nominal working voltage.