Probabilistic delay evaluation in combinational digital circuits by petri nets

This paper primarily focuses on Gate Diffusion Input (GDI) technique used for the implementation of digital logic circuits. It also discusses in detail the limitations and modifications of the basic GDI technique. Initially, GDI was a new technique used for low power digital combinational circuit design. This approach provides a reduction in power consumption, propagation delay, and area of digital circuits while the logic design complexity is small. GDI methodology allows implementation of a wide range of complex logic functions using only two transistors. GDI is a new technique for digital circuits implementation with a lot of advantages over existing ones. This paper also analyzes the recent applications of GDI technique which are the implementation of MASH 1-1 and MOD 2 modulator for Sigma Delta DACs and development of full adders for efficient arithmetic operations.

A backtrack algorithm for the generation of fault location hypotheses in combinational digital circuits is presented. The algorithm uses the results of applied tests and works back from incorrect circuit outputs to generate a list of possible single and/or multiple faults. Suggestions are given for refining the list by selecting probing measurements and by computing the intersection of more than one list resulting from multiple tests.

All optical gate are the main building blocks of all logic circuit in various signal processing devices and circuits. As the need for bandwidth in communication system is increasing day by day SOA (semiconductor optical amplifier) can be a feasible solution for digital signal processing circuits. The semiconductor optical amplifier can be used for the purpose of wavelength conversion, for the synthesis of optical gates, and as comparators in various sequential and combinational digital circuits. In this paper we are a presenting an approach for the realization of universal logic gates NAND, NOR is presented and AND gate is also realized using the same circuits, the results obtained are analyzed on the basis of different values of power through optical power meter and through output time domain waveforms. In this paper nonlinear characteristic of SOA and FWM is utilized to implement various logic functions. The circuit has been implemented successfully at 10Gbps. The proposed scheme is potential approach for applications in future high bit rate optical networks.

In the first part of the chapter, an introduction to the problem of logic level fault simulation is given together with the overview of existing fault simulation techniques. The remaining part of the chapter describes a new approach to fault simulation based on exact critical path tracing to conduct fault analysis in logic circuits. A circuit topology driven computational model is presented which allows not only to cope with complex structures of nested reconvergent fan-outs but also to carry out the fault reasoning for many test patterns concurrently. To achieve the speed-up of backtracing, the circuit is simulated on higher than traditional gate level. As components of the circuit network, fan-out free regions of maximum size are considered, and they are represented by structurally synthesized BDDs. The latter allow to reduce the number of internal variables in the computation model, and therefore to process the whole circuit faster than on the flat gate-level. The method is explained first, for the stuck-at fault model, and then generalized for an extended class of functional fault model covering the conditional stuck-at and transition faults. The method can be used for simulating permanent faults in combinational circuits, and transient or intermittent faults both in combinational and sequential circuits with the goal of selecting malicious faults for injecting into fault tolerant systems to evaluate their dependability. Experimental results are included to give an idea how efficiently the method works with different fault classes.

In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

This paper describes a flexible and systematic implementation method of Petri Nets that can be applied to high speed parallel control. This paper suggests a hard-wired implementation for a high frequency clock-driven system with little jitter. To implement Petri Nets with synchronous (clock-driven) digital circuits, a Synchronous Petri Net is proposed. The suggested implementation method is based on a regular cell-array such as FPGA (field programmable gate array). Radix-k Petri Net and Radix-k conversion are defined to solve technology mapping problem of FPGA that consists of k-size cells. Cell usage, cell utilization, cell complexity, and speed index are defined and derived, which are used for quantitative analysis and efficient design. To help the design process, necessary CAD tools such as design entry library, hard-macro library, and net-list converter are developed. The suggested method is demonstrated using Xilinx FPGA, and its operation is verified by computer simulations.

MixMOS: a mixed-level simulator for digital MOS circuits using a new algebraic approach

As the VLSI technology grows up, optimization is required to reduce the complexity, area and power of the digital circuits. In order to optimize the hardware requirement of digital combinational circuits, evolutionary techniques need to be enforced at various levels such as gate level and device level. This paper presents an efficient approach for the optimal design of a combinational logic circuit with a reduced gate count in MATLAB platform. The evolutionary optimization technique used is Particle Swarm Optimization with Aging Leader and Challenger (ALC-PSO). The results obtained after optimization of Full Subtractor circuit using ALC-PSO technique are shown to have a less number of gates compared to human design method. Later on that optimized circuit has been analysed by DSCH3.5 and Microwind3.1 VLSI CAD Tool. The results shown in this paper reflects that technology scaling decreases the area, delay and power consumption which are some of the major requirements of today's VLSI design.

Petri nets are a well established mod- elling technique for analyzing parallel systems. When coupled with an event-driven operatine system, Petri nets can provide an effective means for integrating and controlling the functions of distributed robotic appli- cations. Recent work has shown that Petri net graphs can also serve as remarkably intuitive operator inter- faces. In this paper the advantages for using Petri net as high-level controllers to coordinate robotic functions will be outlined; the considerations for designing Petri net controllers will be discussed; and simple Petri net structures for implementing an interface for operator supervision will be presented. I. INTRODUCTION The Theory of Intelligent Machines, as proposed in (8), describes a hierarchical organization of the functions of an autonomous robot into three levels: an Execution Level containing the hardware and basic control functions, a Coordination Level integrating the capabilities of the in- telligent machine (IM) across hardware systems, and an Organization Level providing higher-level planning and reasoning capabilities. Figure 1 illustrates this hierarchi- cal organization. An analytic formulation of the theory using information-theoretic measures of uncertainty for each level of the intelligent machine has been developed in recent years 9)(10). A long-term research goal of the ration (CIRSSE) is to attempt, guided by these theories, implementations of autonomous robots. In the past year at CIRSSE a computer architecture was developed that implements the lower two levels of the in- telligent machine (4). The architecture supports an event- Center for Intel I igent Robotic Systems for Space Explc-

Bounded reachability or model checking is widely believed to work poorly when using decision diagrams instead of SAT procedures. Recent research suggests this to be untrue with regards to synchronous systems, particularly digital circuits. This paper shows that the belief is also a myth for asynchronous systems, such as models specified by Petri nets. We propose Bounded Saturation, a new algorithm to compute bounded state spaces using Multi-way Decision Diagrams (MDDs). This is based on the established Saturation algorithm which benefits from a non-standard search strategy that is very different from breadth-first search. To bound Saturation, we employ Edge-Valued MDDs and rework its search strategy. Experimental results show that our algorithm often, but not always, compares favorably against two SAT-based approaches advocated in the literature for deadlock checking in Petri nets.

We present a novel gate-level timing verification method that determines if a combinational circuit satisfies a maximal or a minimal required propagation delay. It is based on computing the greatest fixpoint over a set of equations derived from the gate forward and partial inverse functions, and their interconnections, in the domain of sets of (abstract) waveforms. False negative results can be obtained, however, these can be refined by limited case analysis (based on the analysis of reconvergent fanout). The resolution method is independent of the circuit delay model used, transition or floating mode; only the initial set of waveforms on the primary inputs distinguishes them. The method can accommodate interval gate delays, separate rise and fall transition delays, and component delay correlation.

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Y}_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

The aim of this invited survey is to introduce Computer science/Petri nets specialists to the basic system level issues brought up by the development of Flexible Manufacturing and how Petri nets are used to aid the production engineers in their work. After some terminology concerning production engineering, the hierarchical decision and control level is briefly reviewed. Finally, the role and the presence of nets in CAE (Computer Aided Engineering) and in CAM (Computer Aided Manufacturing) for FMSs (Flexible Manufacturing Systems) are considered. From the design point of view, the use of nets have many advantages in modeling, qualitative analysis, performance evaluation and code generation. From the control of the plant perspective, scheduling on nets models, the coordination of the plant (global and partial) and the presence of nets in the local control level are discussed.Petri nets theory presents a relatively mature body, nevertheless efficient performance evaluation (even for P/T net models) and qualitative analysis of high-level net models still requires important developments. Moreover, the impression that the Petri net newcomer may have looking at the many variants of high-level-nets formalisms may initially produce some kind of rejection. In any case, it is our opinion that Petri nets appears as a key formalism to describe, analyze and implement the control of FMSs. The merging of Petri nets and knowledge based techniques seems to be very promising to deal with large complex discrete event dynamic systems such as FMSs.KeywordsFlexible Manufacture SystemDiscrete Event SystemProgrammable Logic ControllerComputer Integrate ManufactureMarked GraphThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

In this paper a state of the art, main problems and future trends concerning evolutionary design of combinational digital circuits are presented. Several evolutionary algorithms for design and optimization of combinational digital circuits are also shortly described. In evolutionary design methods the main problem is related to "combinatorial explosion" existing in those methods. Because evolutionary design methods are based on "generate and test" model, therefore together with growing of digital circuit input number, the number of potential combinations which must be tested are growing exponentially. This problem is a "bottle-neck" of those methods, and therefore it is discussed in details in this paper. To solve this problem it becomes important to elaborate efficient decomposition techniques of the designed circuits to some less complex sub-circuits, and then to design each of them independently. Also, it is important to create novel genetic operators (as mutation and crossover) which will always lead to acceptable solutions (solutions which satisfy the truth table). Due to such kind of operators, any repair mechanisms need not necessarily be used, and therefore the "generate and test" model will be simplified only to generation of new solutions, and therefore evolutionary design methods will become more effective.

Digital single event transients induced in combinatorial logic are quickly becoming a significant error source as circuit feature sizes shrink and digital circuits operate faster. In this paper, we are able to compare the combinatorial logic error rate to the sequential logic error rate in both heavy ion and proton environments in a simple digital circuit created in a 0.18 /spl mu/m CMOS technology. We are able to do this by comparing data from two unique test chips.