Progress in high-NA EUV lithography towards high-volume manufacturing

As feature sizes continue to shrink, low k1 lithographic processes are required to advance chip technologies. To achieve actual gains in resolution, both the advances in optical systems and imaging capabilities, as well as the improvements in EUV materials and photoresists are key. Researchers today are evaluating the readiness of State-of-the-art materials and processing needed for future applications with 0.33NA exposures at the ASML-imec Advanced Patterning Center, together with studies involving High-NA exposure tools at Lawrence Berkeley National Laboratories and the Paul Scherrer Institute. This talk will give a broad overview of the progress and innovations on high resolution photoresists and patterning processes, and will highlight the key areas of development needed towards high-NA EUV lithography.

In this paper, the role of sub-resolution assist features (SRAFs) in 0.55NA EUV lithography is discussed. We demonstrate how SRAFs help with pattern placement error (PPE) control through exposure focus on horizontal line/space structures using dark field masks. Even for 26nm minimum pitch design rules (relatively high k1), SRAFs help control the focus budget. Next, an analysis of the mask variability budget is done. We establish that a tight CD and placement control on the SRAFs is required for keeping PPE through focus under control. A variability budget of 0.5nm (1X) for both CD and PPE is shown to be just sufficient for maintaining a 40nm depth of focus (DoF) in the absence of process variability. PPE variability due to resist stochastics further reduces the available DoF.

Holistic approaches toward high NA EUV lithography

Implementation of extreme ultra violet lithography (EUVL) for printing features of dimensions around 32nm and below has faced multiple challenges that have been overcome mostly through tool and process engineering. Currently, the main concern for implementation of EUVL in high volume manufacturing is related to stochastic defects, such as line bridges or breaks, which may occur randomly and have an impact on device performance.1 Photon shot noise, in addition to the inherent process variability and material non-homogeneities can lead to defects on the final patterned structures. As the pitch and critical dimension (CD) approach 32nm pitch and below, the dependency of stochastics defects increases exponentially. This paper fits within imec’s EUV stochastics and defectivity program, which investigates the key parameters for the generation and mitigation of defects from both a theoretical and practical approach. Initially, a reference process has been established and a methodology has been developed to capture and characterize bridge-type defects after pattern transfer into relevant layers for metrology and applications. Optical inspection and scanning electron microscopy (SEM) review are used to collect information on the number and types of defects present over large patterned areas (in the order of cm2). With a well-defined inspection technique, experiments related to fundamentals as well as materials and processes are continuously run. In the past years, imec has been leading the fundamental work on stochastic defects.2,3 De Bisschop et al. identified the “defect cliff”, or the exponential dependency of defect density as a function of space CD for multiple parameters, such as resist formulation and exposure/imaging conditions. More recently, the focus has changed to the investigation of the “defect floor”, which as the name suggests, is a flat response of defects to CD. The defect floor suggests that defectivity cannot be further improved, making one of the most relevant problems to solve for implementation of EUV in high volume manufacturing (HVM). Our results show a decomposition of the potential contributors to explore the effect of processing conditions related to scanner, track and pattern transfer on final defect density for a chemically amplified resist and attempt a comparison to a metal-oxide resist. Goal is to understand the contributors to the defect floor and identify an effective route to avoid/minimize defect formation.

Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies. Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development. Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.

The lithographic imaging performance of contact holes is limited by the efficient use of light and contrast fading caused by 3D mask effects. ”Split pupil” exposures have been proposed to mitigate contrast fading for line-space-patterns. We present a simulation study investigating the extendibility of split pupil exposures to dense arrays of contacts on dark field and light field masks using different mask absorber options. Our simulations indicate that the combination of split pupil exposures and low-n/low-k absorbers can offer comfortable imaging performance for arrays of 10 nm square contacts with a pitch of 20 nm on a dark field mask. These results indicate the potential of combining low-n absorbers and split pupil exposure strategies to enable high-NA EUV lithography to reach its ultimate optical resolution limits.

An all-EUV dry resist technology offers a fundamentally new way to enable resist processing targeting differentiating capabilities for high NA lithography. Dry deposition of resists offers stochastic benefits with precise control over thickness and composition. Dry development enables in-situ tuning of development and also improves pattern collapse margin for higher aspect ratios. In this talk, we establish the progress of dry resist development toward extending the limits of single expose with 0.33NA EUV lithography. We assess electrical yield performance with a BEOL Cu-dual damascene test vehicle at aggressive 28nm and 26nm single expose metal pitches and correlate with defect metrology. We also present improvements in 26/28nm pitch line/space patterning and sub-40nm pitch contact hole patterning by optimization of process parameters such as underlayer, bake, dry development and pattern transfer.

High-NA EUV (Extreme Ultraviolet) lithography with a 0.55 numerical aperture (NA) offers enhanced resolution for sub3nm technology nodes. However, its limited exposure field size necessitates multiple stitched exposure fields for large semiconductor designs, leading to stitching-induced variability and potential yield and chip performance loss. This paper presents a comprehensive approach using Place and Route (P&R) techniques to mitigate these challenges. The proposed methodologies include the application of region-specific design rules within stitching boundaries, optimized cell placement and I/O port positioning with stitching awareness, and stitch-aware cell layout optimization. Additionally, cost penalization techniques discourage routing layers from crossing stitch boundaries, and placement blockage controls are introduced to optimize signal routing. Experimental results demonstrate that these approaches mitigate design rule check (DRC) violations, routing congestion, core area overhead, and performance degradation caused by the stitch. The study compares four test cases: (1) a baseline design without stitch-aware methodologies, (2) optimized placement modules and I/O ports incorporating soft blockage, (3) routing allowance within the stitch region with relaxed design rules, and (4) stitch-tolerant standard cell design and placement. By applying these methodologies, DRC overhead due to stitching was reduced from 1,463 to 27, which in turn the area penalty from ~3% to <0.5%, and performance degradation was minimized from ~3% to ~0.2%. The results show that these methods progressively reduce DRC and performance degradation, with the final approach achieving near-complete compensation for High-NA EUV stitch-related losses. These findings highlight the importance of stitch-aware design strategies in ensuring optimal Performance-Power-Area (PPA).

In 2019, finally, extreme ultraviolet (EUV) lithography has been applied to high volume manufacturing (HVM) for preparing advanced semiconductor devices. That was very important year for EUV enthusiasts and semiconductor industry. Because it takes for a long time, more than 30 years, to study EUV lithography for realizing HVM. With recent rapid progress on the source power improvement, EUV lithography development including photoresist materials has been achieved HVM requirements. However, the performance of EUV resist materials are still not enough for the expected HVM requirements, even by using the latest qualifying EUV resist materials. One of the critical issues is the stochastic issues, which will be become ‘defectivity’, like a nano-bridge or a nano-pinching. The analyzing summary of the stochastic factors in EUV lithography, and their improvement status are described in this paper. 2 (two) major stochastic issues, which are photon stochastic and chemical stochastic, were observed in the lithography steps. And the improvement status of each stochastic issues including lithographic results are also described.

Intel's efforts to build a practical quantum computer are focused on developing a scalable spin-qubit platform leveraging industrial high-volume semiconductor manufacturing expertise and 300 mm fabrication infrastructure. Here, we provide an overview of the design, fabrication, and demonstration of a new customized quantum test chip, which contains 12-quantum-dot spin-qubit linear arrays, code named Tunnel Falls. These devices are fabricated using immersion and extreme ultraviolet lithography (EUV), along with other standard high-volume manufacturing (HVM) processes as well as production-level process control. We present key device features and fabrication details as well as qubit characterization results confirming device functionality. These results corroborate our fabrication methods and are a crucial step toward scaling of extensible 2D qubit array schemes.

The following topics are dealt with: low-power electronics; Internet of Things; integrated circuit design; video coding; integrated circuit manufacture; CMOS integrated circuits; field programmable gate arrays; magnetic sensors; calibration; power consumption.

The M3D effect causes telecentricity errors at the illumination slit edges, when the dipole illumination is used for vertical L/S. The telecentricity errors at the right edge and left edge have opposite signs, so they cannot be compensated by changing the sizes of the two poles. The M3D overlay error is defined as the product of the telecentricity error at the illumination slit edge and half the depth of focus. The M3D overlay error depends on the scanner NA and the absorber material. When the conventional Ta absorber is used, the error is negligible for NA 0.33 scanners. It is slightly below the overlay budget for NA 0.55 scanners. However, it exceeds the budget for NA 0.75 scanners. The M3D overlay error becomes larger when PSMs are used. The root cause is the large phase distortion at the absorber sidewalls. The M3D overlay error can be reduced by using binary masks. Binary masks are required for hyper-NA lithography.

Extreme-UV lithography (EUVL) is the most promising candidate of next generation technology for hp20nm node device manufacturing and beyond, however there are many critical issues to solve in the light source, tools, mask and photo resist. Regarding the development of a photo resist, it is necessary for high volume manufacturing (HVM) to improve LWR, resolution limit and sensitivity. Additionally, concerning about deterioration of a patterning performance by Out-of-Band (OoB) light existing in the EUV light, and contamination problem of exposure tool due to the photo resist outgassing are the key issues which have to be resolved toward HVM by EUVL. Especially, the outgassing problem can become a significant issue for fine patterning under high dose exposure condition. This paper proposes the novel solution for these critical issues with the application of a top coat material which is named OBPL (Outgassing & out-of-Band Protection Layer) on photo resist. The key characteristics of OBPL material are to have a role in protection against the OoB adverse effect to keep up the photo resist performance, to suppress the outgassing from photo resist as a barrier layer and to enhance the lithographic performance such as photo resist profile and process window. In designing the OBPL material, the optical property needs having not only the high absorbance of DUV (Deep-UV) light in OoB range but also high transmittance for 13.5nm wavelength to prevent the sensitivity loss. Furthermore, it is found that the polymer backbone affects the outgassing barrier capability in previous evaluation. Based on these investigations, a state-of-the-art OBPL achieves quite a positive lithographic result with sufficient OoB absorption and outgassing suppression. Moreover, this material has applicability to all types of photo resist including NTD (Negative-Tone Development) process. This paper describes the result of the feasibility study for OBPL and the lithography performance with EUV full field scanner.

While extreme ultraviolet lithography (EUVL) is the leading candidate of the next generation lithography, the challenge of managing blank defects must be overcome before EUVL being put to practical use. Besides the efforts of manufacturing defect free blanks, the use of mitigation technique called “pattern shift” is now considered to be a more feasible solution. Whether we aim for defect free blanks or use pattern shift, however, it is quite important to understand the properties of the defects on EUV masks. Of particular interest is to distinguish phase defects from amplitude defects, and pits from bumps. To address the need to understand defect properties, the Actinic Blank Inspection (ABI) high volume manufacturing (HVM) model has acquired a review function using a 1200x magnification optics capable of accurately measuring the size and shape of defects. In this paper, we will discuss how the ABI HVM model classifies defects into pits and bumps.

As it has been widely announced by the leading foundries, and confirmed by ASML, EUV Lithography is being introduced into high volume manufacturing (HVM) since the beginning of this year, in order to enable a more cost-effective manufacturing for the 7nm logic technology node. Very soon, the next technology node will be introduced and the number of EUV layers at 5nm is expected to increase significantly. Although EUV masks are not regarded as the first critical issue for EUV introduction into HVM, several items with respect to EUV masks need more time for improvements, certainly for 5nm and beyond. This presentation will address several mask related items such as EUV pellicle, alternative absorber, EUV mask lifetime, etc... and finally anamorphic masks. This paper is reviewing the status and outlook for these remaining challenges.