PVTA-Aware Performance SRAM Sensor for IoT Applications

CMOS memories occupy a significant percentage of the Integrated Circuits footprint. With the development of new manufacturing technologies to a smaller scale, performance and reliability challenges exist, namely caused by parametric variations such as Process variations (P), power supply Voltage (V) and Temperature (T), and Aging (A) or, in a general perspective, PVTA variations. The purpose of this paper is to present an aging and performance sensor, for CMOS memory cells, namely for SRAM cells, sensing and signaling performance degradation caused e.g. by PVTA variations. The detection strategy consists on the active monitoring on the bit lines the read and write operations performed by the memory cell. In the presence of PVTA degradations, read and write operations have slower transitions, which indicate performance degradation, thus increasing the probability of error occurrence. Hence, when transitions do not occur during the expected time frame, an error signal is flagged to the output due to a slow transition. The sensors' correct operation is demonstrated using SPICE simulations for 65nm and 22nm technologies, allowing to show their effectiveness on monitoring performance and aging degradation on SRAM memory blocks.

Scaling of the on-chip feature size and power supply voltage have significantly reduced the noise margins of an integrated circuit and have aggravated the effects of process and enviromental variations. These effects can introduce delay variations on the signals within a circuit, possibly causing a violation of the timing constraints in a clocked register that can lead to system malfunctioning. The effects of parameter variations on the timing characteristics of adder structures are investigated in this paper. The sensitivity of the critical delay of sum and carry signals under variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different adder architectures.

The electrical performance of an integrated circuit is impacted by (a) environmental factors which include variations in power supply voltage and temperature, and(b) physical factors caused by processing and mask imperfections. Only the physical sources of variability, denoted P, are dealt with. P includes device and wire model parameters such as V/sub th/, T/sub ox/ and R/sub s/.

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on user's requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

Energy efficient computing is one of the primary requirements of ubiquitous battery-operated edge devices including mobile phones, wearables, active implantable medical devices, unmanned aerial, autonomous, and electric vehicles, and hardware modules used in smart IoT infrastructure and cyber-physical systems. One of the primary sources of loss in energy efficiency is the leakage current of logic and memory circuits. In addition, the emergence of on-device intelligence requires a greater number of computations, increased storage per device, and an increased number of operations per watt. Operating circuits at ultra-low voltages including near- and sub-threshold is an effective means to improve the energy efficiency. However, circuit techniques, algorithms, and power management methodologies are required that are tailored to ultra-low voltage operation. Moreover, novel techniques and architectures are needed to improve the overall energy efficiency of circuits that implement neural network models. Techniques to reduce and conserve the leakage current of an IC are, therefore, essential to further minimize the consumed power of a circuit. In this research, novel circuits and algorithms are developed that allow for robust and energy efficient ultra-low voltage operation. Completed research tasks include the development of dynamic differential signaling based logic (DDSL) families, interface circuits that allow for signal propagation between ultra-low voltage and nominal voltage power domains, supply and threshold voltage optimization, and clock-power co-design for sub-threshold operation. The developed DDSL families operate between 400 mV and 450 mV and reduce the total power consumption to 0.96x that of CMOS logic circuits, while improving the performance and noise margin by, respectively, 1.4x and 2.5x. The developed interface circuits include a single ended level shifter and a bidirectional input/output (I/O) circuit, which efficiently convert an input voltage of 450 mV to an output voltage of 3.3 V while consuming only 4.87 mW. The developed clock-power co-design methodology provides a robust power supply voltage of 250 mV to the clock distribution network while assuring resilience to as much as 10% noise on the power network. A novel power management technique defined as 'leakage reuse' is developed to recycle the leakage current from idle circuits or cores and deliver the recycled energy to active circuit blocks or cores. The circuit techniques, scheduling algorithms, and the determination of the energy break-even point are completed for the leakage reuse technique. The power delivery to sub-Vt circuits through leakage reuse reduces the total power consumption to 0.41x that of a conventional power delivery system when generating a supply voltage of 380 mV from the recycled leakage current of circuits operating at 1.2 V. Two scheduling algorithms are developed that allow for the simultaneous execution of power gating and leakage reuse and reduce the total power consumption by 50.2% as compared to a baseline topology that includes neither leakage reuse or power gating. In addition, techniques and methodologies are developed to recycle leakage energy from idle on-chip SRAM memories. Moreover, a novel multi-voltage domain heterogeneous accelerator architecture is developed for energy efficient execution of neural network models. A near-memory computing architecture is developed for the heterogeneous accelerator that leverages the leakage reuse technique applied to an SRAM memory array, where the leakage current of idle memory banks within each processing element is utilized to deliver current to the adjacently placed multiply-and-accumulate (MAC) units. The proposed heterogeneous architecture with leakage reuse results in an energy efficiency of 3.27 tera-operations per second per watt (TOPS/W) as compared to a conventional monolithic and single voltage domain architecture that exhibits an energy efficiency of 0.0458 TOPS/W.

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (V/sub DD/) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation delay to power supply variations is demonstrated for four different register designs. Design modifications are proposed in order to enhance the robustness of each register design under V/sub DD/ variations.

The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAs in time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. This paper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused by neighboring loaded SLICEs or locations in the FPGA. These results were obtained by a method of frequency and delay measurement, capable of delivering stable results in the range of 0.1ps (100fs), using only inexpensive tools and methods.

Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

Internet of Things (IoT) security is becoming important with the growing popularity of IoT devices and their wide applications. Recent network security reports revealed a sharp increase in the type, frequency, sophistication, and impact of distributed denial of service (DDoS) attacks on IoT systems, making DDoS one of the most challenging threats. DDoS is used to commit actual, effective, and profitable cybercrimes. The current machine learning-based IoT DDoS attack detection systems use batch learning techniques, and hence are unable to maintain their performance over time in a dynamic environment. The dynamicity of heterogeneous IoT data causes concept drift issues that result in performance degradation and automation difficulties in detecting DDoS. In this study, we propose an adaptive online DDoS attack detection framework that detects and adapts to concept drifts in streaming data using a number of features often used in DDoS attack detection. This paper also proposes a novel accuracy update weighted probability averaging ensemble (AUWPAE) approach to detect concept drift and optimize zero-day DDoS detection. We evaluated the proposed framework using IoTID20 and CICIoT2023 dataset containing benign and DDoS traffic data. The results show that the proposed adaptive online DDoS attack detection framework is able to detect DDoS attacks with an accuracy of 99.54% and 99.33% for the respective datasets.

With the increasing popularity of the Internet of Things (IoT) platforms, the cyber security of these platforms is a highly active area of research. One key technology underpinning smart IoT systems is machine learning, which classifies and predicts events from large-scale data in IoT networks. Machine learning is susceptible to cyber attacks, particularly data poisoning attacks that inject false data when training machine learning models. Data poisoning attacks degrade the performances of machine learning models. It is an ongoing research challenge to develop trustworthy machine learning models resilient and sustainable against data poisoning attacks in IoT networks. We studied the effects of data poisoning attacks on machine learning models, including the gradient boosting machine, random forest, naive Bayes, and feed-forward deep learning, to determine the levels to which the models should be trusted and said to be reliable in real-world IoT settings. In the training phase, a label modification function is developed to manipulate legitimate input classes. The function is employed at data poisoning rates of 5%, 10%, 20%, and 30% that allow the comparison of the poisoned models and display their performance degradations. The machine learning models have been evaluated using the ToN_IoT and UNSW NB-15 datasets, as they include a wide variety of recent legitimate and attack vectors. The experimental results revealed that the models’ performances will be degraded, in terms of accuracy and detection rates, if the number of the trained normal observations is not significantly larger than the poisoned data. At the rate of data poisoning of 30% or greater on input data, machine learning performances are significantly degraded.

The increasing number of Internet of things (IoT) objects has been a growing challenge of the current spectrum supply. To handle this issue, the IoT devices should have cognitive capabilities to detect and access the unoccupied portion of the wideband spectrum. However, most IoT devices are difficult to perform wideband spectrum sensing using either conventional Nyquist sampling system or sub-Nyquist sampling system since both the power-hungry sampling components and specialized sub-Nyquist sampling hardware are unrealistic in the power-constrained IoT paradigm. In this paper, we propose a blind sub-Nyquist sensing scheme by utilizing the surround IoT devices to jointly sample the spectrum based on the multi-coset sampling theory. Thus, only the off-the-shelf low- rate analog-to-digital converters (ADCs) on the IoT devices are required to form coset samplers and only the minimum number of coset samplers are adopted without the prior knowledge of the number of occupied channels. The experimental results on both the simulated and real-time signals verify the theoretical results and the effectiveness of the proposed scheme. At the meanwhile, it is shown that the adaptive number of coset samplers could be adopted without causing the degradation of the detection performance.

A cross-layer SER analysis in the presence of PVTA variations

Collision-free optimal packet scheduling algorithm for multi-hop wireless IoT networks