Predictive error detection by on-line aging monitoring

The electrical performance of an integrated circuit is impacted by (a) environmental factors which include variations in power supply voltage and temperature, and(b) physical factors caused by processing and mask imperfections. Only the physical sources of variability, denoted P, are dealt with. P includes device and wire model parameters such as V/sub th/, T/sub ox/ and R/sub s/.

Scaling of the on-chip feature size and power supply voltage have significantly reduced the noise margins of an integrated circuit and have aggravated the effects of process and enviromental variations. These effects can introduce delay variations on the signals within a circuit, possibly causing a violation of the timing constraints in a clocked register that can lead to system malfunctioning. The effects of parameter variations on the timing characteristics of adder structures are investigated in this paper. The sensitivity of the critical delay of sum and carry signals under variations in power supply voltage, temperature, and gate oxide thickness is demonstrated for four different adder architectures.

ABSTRACTThis paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit’s delay, power and power–delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

Violations in the timing constraints of a clocked register can cause a synchronous system to malfunction. The effects of variations in the power supply voltage (V/sub DD/) on the timing characteristics of registers are investigated in this paper. The sensitivity of the setup time and data propagation delay to power supply variations is demonstrated for four different register designs. Design modifications are proposed in order to enhance the robustness of each register design under V/sub DD/ variations.

Internet of Things (IoT) applications present significant challenges regarding security, safe operation and power management. In the hardware part of each IoT device, CMOS memories occupy a significant percentage of the Integrated Circuits’ silicon area. With device scaling down, performance and reliability challenges exist, namely caused by parametric variations such as Process (P), power supply Voltage (V) and Temperature (T) variations and Aging (A) or, in a general perspective, PVTA variations. The purpose of this paper is to present a novel, on-line, PVTA-aware performance sensor for CMOS SRAM memory cells, sensing and signaling performance degradation, caused e.g. by PVTA variations. The detection strategy consists on the active monitoring of the bit lines, during the read and write operations. In the presence of PVTA degradations, read and write operations have slower transitions, which indicate performance degradation, thus increasing the probability of error occurrence. Hence, when transitions do not occur during the expected time frame, an error signal is flagged to the output due to a slow transition. The sensor’s correct operation is demonstrated using SPICE simulations for 65 nm and 22 nm technologies, allowing to show its effectiveness on monitoring performance and aging degradation on SRAM memory blocks.

The rapidly growing world of FPGA devices offers important as well as interesting platforms for analyses of process scaling. It creates also new study opportunities in case of new process variations and degradation effects. Changes in parameters of FPGAs in time or under either power supply voltage or temperature variations result in timing variations or delays and may affect the final design quality and dependability. Such timing variations may result in delay faults, up to the final device or equipment malfunction or failure. FPGA designs must be carefully tested and simulated during the design phase. This area is well-covered by many papers and publications and being investigated again with the new processes coming every approximately 2 years. This paper investigates the area of effects caused by the FPGA chip design and metallization or design trade-offs. The paper presents interesting results obtained during various tests including the important values of the total delays caused by neighboring loaded SLICEs or locations in the FPGA. These results were obtained by a method of frequency and delay measurement, capable of delivering stable results in the range of 0.1ps (100fs), using only inexpensive tools and methods.

Rapidly growing portfolio of new technologies in design and manufacturing of advanced integrated circuits allow higher integration of complex structures in ultra-high nano-scale densities. However, the real new devices are sensitive subjects to unacceptable effects of changes of the internal nanostructures. Changes in parameters due to process variations or device aging along the working or its life-time can result in significant in large timing variations or critical BTI-inducted delays and may affect the final design quality and dependability, may result in delay faults, up to the device or equipment malfunction or failure. Also power supply voltage or temperature variations do typically result in significant changes of timing parameters. The presented and tested circuit, method and approach allows extremely simple control of the core voltage during critical operations or during the device lifetime. This paper include also key results of measurement of selected low-power programmable device manufactured using 28 nm low-power TSMC process, a brief comparison to the previous 45 nm LP technology node, as well as a short prediction to the next 22 nm technology node. The presented approach, data and results can also be used in design of various dependable systems.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

A change in voltage at the power node of a gate can significantly increase the delay of a logic gate [32, 498, 499], degrading the overall performance of a system [34]. Since different circuits are affected differently by a drop in the power supply voltage, the power distribution network should be designed to satisfy multiple constraints. The voltage level for those gates along the critical path can tolerate the least voltage degradation, whereas the gates along a noncritical path may satisfy speed constraints despite a higher voltage drop [289]. Circuits, such as a phase-locked loops and voltage controlled oscillators (VCOs), are highly sensitive to changes in the power supply voltage [500]. Alternatively, digital logic circuits can tolerate much higher variations in the power supply voltage. The voltage level of a power distribution network across an entire IC is typically maintained within 10 % degradation, while for a PLL, the voltage level should satisfy a maximum 2 % voltage degradation. To satisfy these constraints, the current supplied to the PLL is filtered by a DC-to-DC converter or a large on-chip decoupling capacitance placed near the PLL [501]. The decoupling capacitors and DC-to-DC converters however consume large area and can dissipate significant power [338].

A method of measuring the losses of a variable air condenser at high frequencies is described in which the condenser under test and the standard are connected in series as part of a tuned circuit. A radio-frequency voltage of resonant frequency is impressed on this circuit for a stated value of the standard. The unknown is then removed and the standard adjusted to resonance. The voltage across the tuned circuit is readjusted to its initial value by placing a conductance across the standard. The design of the standard condenser requires special considerations which are discussed. A self-biasing valve voltmeter, which is not critical to variations in power-supply voltage, is used. The results of measurements on several specimen condensers are given. A method of extending the measurements to higher frequencies is shown.

In this paper, scalable driver I/O macromodels have been proposed for efficient signal integrity and timing analysis of today's high-speed systems. Variations in semiconductor process, temperature, and power supply voltage affect the output voltage and current in driver circuits. The effect of these variations on driver and receiver circuits has been captured using Lagrange's interpolation technique. In this paper, scalable macromodeling approach has been applied to differential driver circuits and single-ended driver and receiver circuits. Scalable driver and receiver circuits consume less CPU memory and simulation time compared to transistor-level driver and receiver circuits. The accuracy of scalable macromodels has been tested on various test cases for differential driver and single-ended driver-receiver circuits and results yielded good accuracy.

State-of-the-art variants of slotted Aloha (S-Aloha) for underwater acoustic networks do not consider the joint effect of retransmission and distance-dependent propagation delay variability, which is one of the most important parameters that affect the performance of any medium access control protocol. In this study, the authors analyse the stability of S-Aloha in a network environment, such as underwater, where propagation delay and its variance are not negligible. A finite number of unbuffered transmitters are considered. Through mathematical analysis, supported by discrete event simulations, they compare the utilisation and stability with S-Aloha in radio frequency environments where propagation delay, as well as delay variance, are negligible. The comparison results indicate that the stability region is appreciably shifted and also there is a significant decrease of utilisation in the presence of retransmission and distance-dependent propagation delay variability.

Performance analysis of broadcast star network with collision-avoidance switch

In this paper, we have compared and analyzed two architectures of implicit pulsed triggered flip-flop (P-FF). The Predictive Technology Model (PTM) 45nm and 32nm technology nodes are used for simulations. The variation in delay and power for both architectures with respect to variation in supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) and temperature is analyzed. Results from simulations at 45nm show that design with conditional pulse-enhancement technique (CPE) is better in terms of power consumption whereas design using gated-pull up control (GPC) is less prone to temperature and supply voltage variation. Similar trends have been noticed at a 32nm technology node.