A Comparative Study of Pulse Triggered Flipflops

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature.

A CMOS low voltage bandgap reference circuit is presented. The proposed circuit architecture enables it to work with supply voltages as low as 1.1 V. The circuit is designed in 90 nm CMOS technology for a typical bandgap output voltage of 611 mV. Simulation results show that generated bandgap output voltage varies from 600 mV to 626 mV across all possible combinations of MOSFET, resistor, BJT, supply voltage and temperature variation corners. Simulation results have been given for a wide temperature variation from -40C to 125C and supply voltage variation from 1.1 V to 1.3 V.

With aggressive CMOS technology scaling, Negative Bias Temperature Instability (NBTI) has emerged as one of the major system lifetime reliability threats, which gradually increases PMOS transistor threshold voltage and hence results in increased circuit delay. NBTI-induced performance degradation depends heavily on time-varying parameters such as temperature, duty cycle and supply voltage. Previous analytical models for NBTI effects, however, cannot cover all these parameters, causing overly optimistic or overly pessimistic analysis. In this work, we propose a comprehensive NBTI analytical model that explicitly takes supply voltage, duty cycle and temperature variations into consideration. The accuracy of the proposed model is validated against cycle-accurate simulation for NBTI effects. In addition, based on the proposed model, we present an efficient simulation framework for system lifetime prediction by running representative workloads only. Experimental results demonstrate the efficacy and efficiency of the proposed solution.

Process, voltage and temperature (PVT) variations in emerging ultra-deep submicron (UDSM) technology nodes critically affect device performances and limit further scaling of such devices based on Moore's law. This paper proposes CNFET-based design of robust Schmitt trigger circuits, which outperform their CMOS counterparts in terms of mean values as well as variabilities of all considered design metrics. Popular Schmitt trigger designs are investigated and a comparative analysis is carried out based on Monte Carlo simulations in an HSPICE environment, using the 16-nm CMOS Predictive Technology Model (PTM), to choose the designs with best performance in terms of variability of design metrics such as power, power-delay product (PDP) and hysteresis width. These are then re-designed with corresponding optimized devices using the experimentally validated Stanford University CNFET model. The proposed CNFET-based circuits provide a 9.9×, 11.8× and 22× improvement in power, PDP and hysteresis width variability respectively, while also providing better noise immunity through increased hysteresis widths, thus demonstrating their superiority to CMOS circuits in all respects at highly scaled technology nodes.

In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

In the applications of biometric authentication and video surveillance, the image sensor is expected to provide certain degree of trust and resiliency. This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that involves image sensor as a trusted entity. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures. The proposed differential readout stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations. The threshold of difference can be tightened to winnow out more unstable response bits from the challenge-response space offered by modern image sensors to enhance the reliability under harsher operating conditions and loosened to improve its resiliency against masquerade attacks in routine operating environment. The proposed design can be classified as a weak PUF which is resilient to modeling attacks, with direct access to its challenge-response pair restricted by the linear feedback shift register. Our experiments on the reset voltages extracted from a 64 × 64 image sensor fabricated in 180 nm 3.3 V CMOS technology demonstrated that robust and reliable challenge-response pairs can be generated with a uniqueness of 49.37% and a reliability of 99.80% under temperature variations of 15∼ 115°C and supply voltage variations of 3∼ 3.6V

The electrical performance of an integrated circuit is impacted by (a) environmental factors which include variations in power supply voltage and temperature, and(b) physical factors caused by processing and mask imperfections. Only the physical sources of variability, denoted P, are dealt with. P includes device and wire model parameters such as V/sub th/, T/sub ox/ and R/sub s/.

Process variation is an obstacle in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common transconductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We develop the background theory of the scheme and present its performance across process corners. We further apply our scheme to two well known amplifier topologies in the TSMC 65 nm CMOS process as design examples-an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). Measured results over 100 chips of the LNA show that our compensation technique reduces variation in gain by a factor of 3.7× compared to the baseline case. The CSA exhibits similar reductions in gain variation across 88 measured chips. We also present measured results demonstrating how our technique alleviates voltage gain variations caused by temperature and supply voltage changes.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

In this work, a novel digital leaky integrate-and-fire neuron design is proposed as part of a charge-trap transistor (CTT)-based neuromorphic system. CTTs, which are compute-in-memory devices, are used to realize the synaptic array of the neuron and support weight multiplication operations for incoming pulse signals. The proposed digital neuron does not rely on a capacitor for accumulation, making it area-efficient and scalable, and thus useful for design of large spiking neural networks. The neuron accumulates the weighted inputs from the synaptic array and generates an outgoing pulse, i.e., fires, when a pre-set threshold is reached. The digital neuron includes a sampler circuit, multi-level comparator, pulse generator, leaky circuit, 3-bit counter, and digital comparator circuit. Since the circuit is digital, the design is robust to noise, mismatch, and process, voltage, and temperature variations. The digital neuron is designed in GF 22 nm FDSOI technology, operates at a supply voltage of 0.8 V, and occupies an area of 33.5 μ m2. The neuron was simulated, including under temperature and supply voltage variations, and exhibits expected functionality.

Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of FPGAs (which arises due to their flexible structure), make them less appealing for extreme low power applications. In this paper, we present a design of an FPGA look-up table (LUT), with the goal of seamless operation over a wide band of supply voltages. The same LUT design has the ability to operate at sub-threshold voltage when low power is required, and at higher voltages whenever faster performance is required. The results show that operating the LUT in sub-threshold mode yields a (~80x) lower power and (~4x) lower energy than full supply voltage operation, for a 6-input LUT implemented in a 22nm predictive technology. The key drawback of sub-threshold operation is its susceptibility to process, temperature, and supply voltage (PVT) variations. This paper also presents the design and experimental results for a closed-loop adaptive body biasing mechanism to dynamically cancel these PVT variations. For the same 22nm technology, we demonstrate that the closed-loop adaptive body biasing circuits can allow the FPGA to operate over an operating frequency range that spans an order of magnitude (40 MHz to 1300 MHz). We also show that the closed-loop adaptive body biasing circuits can cancel delay variations due to supply voltage changes, and reduce the effect of process variations on setup and hold times by 1.8x and 2.9x respectively.

The purpose of this paper is to present a predictive error detection methodology, based on monitoring of long-term performance degradation of semiconductor systems. Delay variation is used to sense timing degradation due to aging (namely, due to NBTI), or to physical defects activated by long lifetime operation, which may occur in safety-critical systems (automotive, health, space). Error is prevented by detecting critical paths abnormal (but not fatal) propagation delays. A monitoring procedure and a programmable aging sensor are proposed. The sensor is selectively inserted in key locations in the design and can be activated either on user's requirement, or at pre-defined situations (e.g., at power-up). The sensor is optimized to exhibit low sensitivity to PVT (Process, power supply Voltage and Temperature) variations. Sensor limitations are analysed. A new sensor architecture and a sensor insertion algorithm are proposed. Simulation results are presented with a ST 65 nm sensor design.

The design optimization for digital circuits built with gate-all-around silicon nanowire transistors (SNWTs) is discussed in details. Based on the verified multiwire SNWT compact model with accurate parasitic capacitance and resistance modeling, the design consideration of SNWT digital circuits (SNWTCs) at a 16-nm technology node, such as the SNWT ring oscillator (SNWT-RO), is discussed with the optimization of key process and layout parameters in the multiwire SNWT. In order to reduce the parasitic components of SNWTs and improve SNWTCs' performance (including delay, power, and layout area), process (including nanowire diameter and other related parameters) and layout parameters (including wire number per transistor and footprint width of SNWTs) should be carefully designed. Through design optimization, the total capacitance and parasitic resistance of the SNWT can be reduced by over 80% compared with nonoptimized parasitic components, which leads to more than 90% reduction of circuit-level delay and power. Furthermore, the design optimization is carried out for power-driven design and area-driven design, respectively. For each case, the SNWT-RO with fan-out of 1 loading and 4 loading is optimized with variable power supply voltage for optimization. The optimized layout parameters for power-driven design and area-driven design are obtained, which can provide useful guidelines for SNWTC design.

In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

This paper presents a thermal sensing and VLSI thermal management scheme using an array of on-chip all-digital delay-line based temperature sensors. A fully digital self-calibration method that removes the temperature sensors' sensitivities to supply voltage and process variations is proposed. The proposed calibration method assigns a unique correction factor, N C to each sensor, making all the sensors' calibrated outputs to be the same at start-up. The correction factor is updated when supply voltage variations are detected. Only one calibration block is required to calibrate multiple delay-line based temperature sensors sequentially. For each additional sensor, only additional registers for storing N C are required. The proposed self-calibrated temperature sensors are demonstrated on an Altera Cyclone IV FPGA based VLSI thermal management system. Runtime thermal profiles for four cores mapped on the Cyclone IV FPGA chip using a hybrid dynamic thermal management (DTM) method are obtained. The percentage of time that each core spent in a particular temperature range is plotted in a histogram. A comparison of different DTM techniques demonstrates that the proposed hybrid DTM reduces the amount of time that the MPSoC spent at higher temperatures and larger thermal gradients, by 10% and 21%, respectively. In addition, the proposed hybrid DTM offers a 10% improvement in the average processing rate (instructions per second) when compared with the conventional global DFS approach.