Digital LIF Neuron for CTT-Based Neuromorphic Systems

With aggressive CMOS technology scaling, Negative Bias Temperature Instability (NBTI) has emerged as one of the major system lifetime reliability threats, which gradually increases PMOS transistor threshold voltage and hence results in increased circuit delay. NBTI-induced performance degradation depends heavily on time-varying parameters such as temperature, duty cycle and supply voltage. Previous analytical models for NBTI effects, however, cannot cover all these parameters, causing overly optimistic or overly pessimistic analysis. In this work, we propose a comprehensive NBTI analytical model that explicitly takes supply voltage, duty cycle and temperature variations into consideration. The accuracy of the proposed model is validated against cycle-accurate simulation for NBTI effects. In addition, based on the proposed model, we present an efficient simulation framework for system lifetime prediction by running representative workloads only. Experimental results demonstrate the efficacy and efficiency of the proposed solution.

A CMOS low voltage bandgap reference circuit is presented. The proposed circuit architecture enables it to work with supply voltages as low as 1.1 V. The circuit is designed in 90 nm CMOS technology for a typical bandgap output voltage of 611 mV. Simulation results show that generated bandgap output voltage varies from 600 mV to 626 mV across all possible combinations of MOSFET, resistor, BJT, supply voltage and temperature variation corners. Simulation results have been given for a wide temperature variation from -40C to 125C and supply voltage variation from 1.1 V to 1.3 V.

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature.

Process variation is an obstacle in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common transconductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We develop the background theory of the scheme and present its performance across process corners. We further apply our scheme to two well known amplifier topologies in the TSMC 65 nm CMOS process as design examples-an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). Measured results over 100 chips of the LNA show that our compensation technique reduces variation in gain by a factor of 3.7× compared to the baseline case. The CSA exhibits similar reductions in gain variation across 88 measured chips. We also present measured results demonstrating how our technique alleviates voltage gain variations caused by temperature and supply voltage changes.

In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

In the applications of biometric authentication and video surveillance, the image sensor is expected to provide certain degree of trust and resiliency. This paper presents a new low-cost CMOS image sensor based physical unclonable function (PUF) targeting a variety of security, privacy and trusted protocols that involves image sensor as a trusted entity. The proposed PUF exploits the intrinsic imperfection during the image sensor manufacturing process to generate unique and reliable digital signatures. The proposed differential readout stabilizes the response bits extracted from the random fixed pattern noises of selected pixel pairs determined by the applied challenge against supply voltage and temperature variations. The threshold of difference can be tightened to winnow out more unstable response bits from the challenge-response space offered by modern image sensors to enhance the reliability under harsher operating conditions and loosened to improve its resiliency against masquerade attacks in routine operating environment. The proposed design can be classified as a weak PUF which is resilient to modeling attacks, with direct access to its challenge-response pair restricted by the linear feedback shift register. Our experiments on the reset voltages extracted from a 64 × 64 image sensor fabricated in 180 nm 3.3 V CMOS technology demonstrated that robust and reliable challenge-response pairs can be generated with a uniqueness of 49.37% and a reliability of 99.80% under temperature variations of 15∼ 115°C and supply voltage variations of 3∼ 3.6V

The scaling trend of semiconductor devices has raised several issues such as energy consumption and heat dissipation, as well as the increasing probabilistic behavior of devices. Motivated by the necessity to consider probabilistic approaches to future designs, probabilistic CMOS (PCMOS) based computing has been proposed. PCMOS devices are inherently probabilistic devices that compute correctly with a probability <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> . This paper investigates the tradeoffs between the energy, speed (or performance), and probability of correctness ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> ) of PCMOS circuits. For given constraints on <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> , performance, and energy delay product (EDP), and using analytical models of energy, delay, and <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> , the optimum values of EDP and probability are found for PCMOS circuits. The analytical models are validated using circuit simulations for PCMOS circuits designed in a 0.13-mum process. The results show that, to minimize EDP, it is preferable to operate PCMOS circuits at lower supply voltages. On the other hand, to maximize <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> , the highest possible supply voltage under the given constraints is preferable. Our analysis makes it possible to achieve an optimal circuit design that satisfies the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">p</i> , performance, and EDP requirements for a given application. An analysis of the impact of variations in temperature, threshold voltage, and supply voltage on optimal EDP and probability values is also included.

The use of low carbon steel is categorized as one of the supporting materials in industrial and technological developments because it has high ductility and toughness. However, low carbon steel has limitations in terms of corrosion resistance. There are several ways to increase corrosion resistance in steel. One of them is by providing a layer of protection on the steel surface. The steel plating method used is the electrolysis method or electroplating method. This study aims to determine the influence of variations in current, voltage, temperature, and time on the thickness of the coating formed on steel. The steel plating process is carried out by electroplating process where the coating material or anode is Nickel (Ni) with dimensions (60 mm x 30 mm x 0,1 mm). In comparison, the coated object or cathode is SK5 steel with dimensions (50 mm x 20 mm x 0,3 mm). The aim of this study is to investigate the effect of Current, Voltage, Temperature, and Time Variations on the thickness of steel using electroplating processes. Moreover, all factors will be optimised to achieve the best thickness for steel. Consequently, the corrosion resistance of SK5 can be significantly improved by increasing its thickness. The current variations were used 1A, 2A, 3A, and 4A; voltage variations were used 3V, 6V, 9V, and 12V; temperature variations were used 30°C, 40°C, and 50°C; and times variations were used 0 m, 5 m, 10 m, and 20 m. Based on the results of research that has been carried out on all samples, it is concluded that current, voltage, temperature and time affect the thickness of the sample in the electroplating process. The current, voltage, temperature and time values are linearly related to the thickness resulting from the electroplating process.

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.

In this paper, we have compared and analyzed two architectures of implicit pulsed triggered flip-flop (P-FF). The Predictive Technology Model (PTM) 45nm and 32nm technology nodes are used for simulations. The variation in delay and power for both architectures with respect to variation in supply voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) and temperature is analyzed. Results from simulations at 45nm show that design with conditional pulse-enhancement technique (CPE) is better in terms of power consumption whereas design using gated-pull up control (GPC) is less prone to temperature and supply voltage variation. Similar trends have been noticed at a 32nm technology node.

A bipolar integrated piezoresistive-type silicon pressure sensor with frequency-modulated output where frequency is related to the applied pressure has been developed. The sensor peripheral circuits were fabricated in a standard bipolar process and the shaping of the sensor was accomplished using an EDP anisotropic etchant. Signal conditioning circuitry consists of a band-gap voltage reference circuit, a differential amplifier, and a current-controlled oscillator. This circuit is designed to stabilize change in sensitivity due to variations in temperature and supply voltage.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

An on-chip sub-μW RC oscillator suitable for ultra-low power applications is presented. A technique that cancels both comparator delay and offset are proposed to improve the frequency stability against variations of temperature and supply voltage. This relaxation oscillator is designed and simulated in a 180-nm CMOS technology. The post layout simulation results show that the proposed circuit has a 1-cycle start-up time, and the frequency drift is less than ±0.6%. For the supply voltage changing from 0.9 to 1.2 V, the variation of frequency is −0.72%–+0.68% and the temperature coefficient is 75.5 ppm/°C over 0 to 90°C. The power consumption of the proposed oscillator is 255 nW at TT and 27°C.

A bipolar integrated silicon pressure sensor

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

The method of ldquoLogical Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0degC to 125degC, and increases 2X while supply voltage decreasing from 1 V to 0.5 V in 90nm process. Thus a simple linear extended logical effort g, 1/g=(m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> t+b <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> )V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> +C, supporting for temperature t and supply voltage VDD variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.