An All CMOS Current Reference

We propose a simple current reference circuit with low power supply voltage dependence and low temperature coefficient by combining output currents of conventional current mirror and Nagata current source. Detailed analysis and design procedure are presented. Preliminary test chip measurement results are also represented. Temperature dependence of the output current was compensated by synthesizing required temperature coefficient of a resistor from different types of on chip resistors. The output current indicated +200 ppm/deg temperature coefficient by circuit simulation, and is an order of improvement over without temperature compensation case. The proposed current reference circuit does not have positive feedback loop, thus, it is free from start-up problem unlike beta-multiplier. Design example indicated far better performance against power supply voltage change and temperature change than simple current mirror.

Invasive biomedical applications involving acquisition and recording of biological signals require current reference generation circuits for low voltage front-end amplifier and filter circuits. However, achieving current reference using Self-Biased Current Source (SBCS) for these circuits at same low supply voltages poses requirement of resistors. In this work, we compare the effect of passive poly resistor and Composite Triode MOS Resistor (CTMR) on the performance of low voltage SBCS circuit using 0.18 µm standard SCL foundry process parameters and models of MOS, capacitor and resistor. For current reference generation of 371 nA, the temperature coefficient (ppm/degree Celsius) values for passive poly resistor and CTMR are 2400 and 2251 respectively. The Figure of Merit, FOM (ppm/degree Celsius) and Coefficient of variance (CV) at different process corners with Monte-carlo simulation (MCS) runs of 100 for CTMR are 0.93 and 0.16 times lower than that of passive poly resistor. The CTMR based SBCS is anticipated to be used in low voltage front-end biomedical applications.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35 µm CMOS process demonstrate that a temperature coefficient of 10.2 ppm/°C is realised with temperature ranging from −40°C to 140°C, and a power supply rejection ratio of 58 dB is achieved with a maximum supply current of 27 µA. The active area of the presented BGR is 160 × 140 µm2.

With aggressive CMOS technology scaling, Negative Bias Temperature Instability (NBTI) has emerged as one of the major system lifetime reliability threats, which gradually increases PMOS transistor threshold voltage and hence results in increased circuit delay. NBTI-induced performance degradation depends heavily on time-varying parameters such as temperature, duty cycle and supply voltage. Previous analytical models for NBTI effects, however, cannot cover all these parameters, causing overly optimistic or overly pessimistic analysis. In this work, we propose a comprehensive NBTI analytical model that explicitly takes supply voltage, duty cycle and temperature variations into consideration. The accuracy of the proposed model is validated against cycle-accurate simulation for NBTI effects. In addition, based on the proposed model, we present an efficient simulation framework for system lifetime prediction by running representative workloads only. Experimental results demonstrate the efficacy and efficiency of the proposed solution.

A CMOS low voltage bandgap reference circuit is presented. The proposed circuit architecture enables it to work with supply voltages as low as 1.1 V. The circuit is designed in 90 nm CMOS technology for a typical bandgap output voltage of 611 mV. Simulation results show that generated bandgap output voltage varies from 600 mV to 626 mV across all possible combinations of MOSFET, resistor, BJT, supply voltage and temperature variation corners. Simulation results have been given for a wide temperature variation from -40C to 125C and supply voltage variation from 1.1 V to 1.3 V.

In this work, a novel digital leaky integrate-and-fire neuron design is proposed as part of a charge-trap transistor (CTT)-based neuromorphic system. CTTs, which are compute-in-memory devices, are used to realize the synaptic array of the neuron and support weight multiplication operations for incoming pulse signals. The proposed digital neuron does not rely on a capacitor for accumulation, making it area-efficient and scalable, and thus useful for design of large spiking neural networks. The neuron accumulates the weighted inputs from the synaptic array and generates an outgoing pulse, i.e., fires, when a pre-set threshold is reached. The digital neuron includes a sampler circuit, multi-level comparator, pulse generator, leaky circuit, 3-bit counter, and digital comparator circuit. Since the circuit is digital, the design is robust to noise, mismatch, and process, voltage, and temperature variations. The digital neuron is designed in GF 22 nm FDSOI technology, operates at a supply voltage of 0.8 V, and occupies an area of 33.5 μ m2. The neuron was simulated, including under temperature and supply voltage variations, and exhibits expected functionality.

Process variation is an obstacle in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common transconductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We develop the background theory of the scheme and present its performance across process corners. We further apply our scheme to two well known amplifier topologies in the TSMC 65 nm CMOS process as design examples-an inductive degenerated low-noise amplifier (LNA) and a common source amplifier (CSA). Measured results over 100 chips of the LNA show that our compensation technique reduces variation in gain by a factor of 3.7× compared to the baseline case. The CSA exhibits similar reductions in gain variation across 88 measured chips. We also present measured results demonstrating how our technique alleviates voltage gain variations caused by temperature and supply voltage changes.

A CMOS process-insensitive voltage reference generator, which is based on the weighted sum of thermal voltage and difference of threshold voltages, is presented. The voltage reference circuit uses high VTH and regular VTH transistors and produces reference level of 422mV. The proposed technique is analyzed theoretically and its results are compared with other methods. The circuit is designed and simulated in standard 180nm mixed mode CMOS technology for low-cost low-power applications. The circuit operates at minimum supply voltage of 1V with maximum drawn current of 577nA only. A temperature coefficient of 36ppm/°C is achieved with line sensitivity of 0.01%/V. The proposed reference generator exhibits PSRR of -60.34 dB and -37.09 dB at 100Hz and 1MHz, respectively.

Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

This paper presents a novel low-voltage single stage CMOS RF Variable Gain Amplifier (RFVGA) designed in 130 nm IBM CMOS process technology using current feed-back gain-independent impedance matching. The proposed RFVGA has a nearly constant gain over the 400 MHz–1 GHz frequency band. Also, it has a 70 dB gain variation (-40 dB to 30 dB) which is decibel-linear within this frequency band for a control voltage in the range of 0.41 V–0.81 V. The RFVGA demonstrates high linearity (THD ≈ -60 dB) and noise immunity (average Noise Figure ≤ 6 dB). It has an input referred third-order intercept point (IIP3) of -1.5 dBm, and an input reflection coefficient (S11) under -8 dB within the frequency band of interest. Also, it dissipates around 5 mW using a 1.2 V power supply. Further, Monte Carlo simulations incorporating process, supply voltage and temperature variations (PVT variations) as well as mismatch between devices (based on width and length of devices) indicate that the design is quite robust. The proposed RFVGA is highly suitable for mobile digital television (DTV) tuner applications.

An on-chip sub-μW RC oscillator suitable for ultra-low power applications is presented. A technique that cancels both comparator delay and offset are proposed to improve the frequency stability against variations of temperature and supply voltage. This relaxation oscillator is designed and simulated in a 180-nm CMOS technology. The post layout simulation results show that the proposed circuit has a 1-cycle start-up time, and the frequency drift is less than ±0.6%. For the supply voltage changing from 0.9 to 1.2 V, the variation of frequency is −0.72%–+0.68% and the temperature coefficient is 75.5 ppm/°C over 0 to 90°C. The power consumption of the proposed oscillator is 255 nW at TT and 27°C.

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature.

Field programmable gate arrays (FPGAs) are the implementation platform of choice when it comes to design flexibility. However, the high power consumption of FPGAs (which arises due to their flexible structure), make them less appealing for extreme low power applications. In this paper, we present a design of an FPGA look-up table (LUT), with the goal of seamless operation over a wide band of supply voltages. The same LUT design has the ability to operate at sub-threshold voltage when low power is required, and at higher voltages whenever faster performance is required. The results show that operating the LUT in sub-threshold mode yields a (~80x) lower power and (~4x) lower energy than full supply voltage operation, for a 6-input LUT implemented in a 22nm predictive technology. The key drawback of sub-threshold operation is its susceptibility to process, temperature, and supply voltage (PVT) variations. This paper also presents the design and experimental results for a closed-loop adaptive body biasing mechanism to dynamically cancel these PVT variations. For the same 22nm technology, we demonstrate that the closed-loop adaptive body biasing circuits can allow the FPGA to operate over an operating frequency range that spans an order of magnitude (40 MHz to 1300 MHz). We also show that the closed-loop adaptive body biasing circuits can cancel delay variations due to supply voltage changes, and reduce the effect of process variations on setup and hold times by 1.8x and 2.9x respectively.

An ultralow-power direct-conversion Bluetooth-low-energy (BLE) receiver (RX) front-end that employs current-reuse and subthreshold techniques is presented. A stacked and self-biased low-noise amplifier (LNA) with active balun consumes 400 μW and achieves a noise figure (NF) of 3.2-dB and a high gain (programmable from 18 to 31 dB), meeting the system specifications over the process, supply voltage, and temperature (PVT) variations. The RX front-end has a measured integrated NF of 5.2 dB from 50 KHz to 1 MHz that corresponds to a sensitivity of -95.1 dBm. At an RX gain of 47 dB, IIP3 was measured at -19.7 dBm. The LC VCO operates at twice the carrier frequency with a tuning range of 4.55 to 5.15 GHz in an integer-N phase-locked loop (PLL). An ultralow-power CML divider is used to generate the LO I/Q. The integrated phase noise (IPN) of the LO at 2.4 GHz is 0.83° with spot phase noise of -119.9 dBc/Hz at 3 MHz frequency offset. The PLL is entirely placed inside the VCO inductor resulting in an overall die area reduction of 8%. A 6- μW automatic dc offset-calibrator avoids saturation of consecutive baseband blocks. Multiple μW-level feedback control loops are used in the design to make it robust over PVT variations. The RX front-end prototype is implemented in a 40-nm LP CMOS process and occupies a silicon area of 0.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .