Current Reference Circuit Operable at Low Voltages Using Composite MOS Triode Resistor

This paper presents a gate-leakage-based supply- and temperature-stabilized current reference generator that can output currents as low as 5 pA with minimal power overhead. The output reference current is generated by driving a set of gate-leakage transistors designed to have opposing temperature coefficients with a stabilized voltage reference. Low-power operation is achieved by generating the voltage reference via a novel two-stage, 4T push-pull structure that can operate at a low supply voltage, and driving this reference to the gate-leakage transistors via a low-voltage self-biased amplifier. Designed in a 65 nm CMOS process, the proposed current reference generator is simulated to consume 14.5 pW at a 0.5 V supply voltage. Due to the push-pull structure and complementary gate-leakage transistors, the design achieves a temperature stability of 31 ppm/°C from 0 °C to 100 ° C, and a line sensitivity of 0.94%/V averaged across 500 Monte Carlo samples, thereby enabling an ultra-low-power, area-efficient, and temperature- and supply-stabilized current reference solution at pA-levels.

In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35 µm CMOS process demonstrate that a temperature coefficient of 10.2 ppm/°C is realised with temperature ranging from −40°C to 140°C, and a power supply rejection ratio of 58 dB is achieved with a maximum supply current of 27 µA. The active area of the presented BGR is 160 × 140 µm2.

A novel scheme for a CMOS low-voltage reference is proposed. It uses current subtraction between the currents generated by two instances of the same current generator circuit, each one configured with different magnitude and temperature coefficients. Temperature stability is achieved owing to the partial compensation of the MOSFET threshold voltage and mobility temperature effects. For a nominal reference voltage of 436.5 mV, SPICE simulation reveals a ±38.2 ppm/°C temperature coefficient within the range of -20 °C to 100°C.

In this paper, a MOSFET-only voltage reference with novel curvature-compensation is proposed. In order to reduce the temperature coefficient in the proposed voltage reference, two proportional to absolute temperature voltages with opposite second-order order TC are added on a threshold voltage, which is achieved by a resistorless threshold voltage extractor. Besides, self-biased current source with feedback is realized at the same time, which can provide bias current for the whole voltage reference and enhance the performance of generated voltage reference without additional power consumption. Verification results of the proposed voltage reference implemented with 0.35µm technology process show that the temperature coefficient is 2.4 ppm/□ with a temperature range of −20□ to 80□ is obtained, and a 62.9 dB power supply rejection ratio is achieved with a 68nA maximum supply current.

This paper proposes a current source-type pulse generator circuit to improve load voltage waveforms by solving the voltage ringing problem of capacitively coupled plasma systems. The voltage source-type pulse power supplies used in the plasma industry have short-circuit currents and voltage ringing problems with capacitively coupled plasma loads. The current source-type pulse generator proposed in this paper can solve these problems. The proposed circuit consists of four detailed circuits: bias current generator, bias current modulator, slope current generator, and slope current modulator. They form two constant currents at the DC link, and output two pulse currents to the load. These output currents contribute to generating the plasma load voltage required by the capacitively coupled plasma process. The proposed circuit is verified by a PLECS simulator and a laboratory-scale hardware system. To check the improvement of the output waveform, a voltage source-type pulse generator and the current source-type pulse generator are tested under the same experimental conditions. The results are represented by load voltage and current waveforms. In addition, the entire system of the current source-type pulse generator is designed and verified by simulation and experimental results. The resulting output waveforms meet the process requirements, and the obtained results demonstrate that the proposed current source-type pulse generator circuit can be suitably used for capacitively coupled plasma loads.

Current reference circuits are widely used in analog integrated circuit design. However, due to PVT and aging variations, the reference currents are mostly affected which requires reprogramming the reference circuit. Recently, memristors are investigated in many analog applications due to the programmability and non-volatility. In this paper, we introduce a simple programmable memristor-based circuit that can be used in current reference generators. The circuit is based on one memristor and one CMOS transistor to tune the resistance of the memristor. VTEAM memristor model is used to study the proposed circuit programmability. The necessary tuning conditions for the circuit are discussed. Then, the proposed circuit have been used in the well-known Beta-Multiplier current reference to generate a programmable current reference. The designed circuit has a reasonable current tuning range due to the limited range of the used memristor model. Different circuit simulations are provided using ST 65nm CMOS Technology.

This paper presents a self-tuning filter (STF)-based adaptive linear neuron (ADALINE) reference current generation algorithm to enhance the operation of a three-phase three-level neutral-point diode clamped (NPC) inverter-based shunt active power filter (SAPF) under non-ideal (unbalanced and/or distorted) source voltage conditions. SAPF is an effective and versatile mitigation tool for current harmonics. As for its controller, ADALINE-based reference current generation algorithmd have widely been applied and proven to work effectively under balanced and purely sinusoidal source voltage conditions. However, no work has been conducted to study its performance under non-ideal source voltage conditions. In this work, a STF-based fundamental voltage extraction algorithm is integrated with an ADALINE algorithm, serving as synchronizer algorithm to ensure in-phase operation of the generated reference current with the non-ideal source voltage. Hence, it completely eliminates any dependency on conventional synchronizer algorithms such as phase-locked loop (PLL) and zero-crossing detector (ZCD). Additionally, the proposed STF-based ADALINE algorithm implements the modified Widrow-Hoff (W-H) weight updating algorithm for fast generation of reference current. Both simulation and experimental works are performed to verify design concept and effectiveness of the proposed algorithm. Comparative study with another recently reported algorithm is performed to investigate the performance improvement achieved by SAPF while using the proposed algorithm.

A low voltage low power operational transconductance amplifier (OTA) based on a bulk driven cell and its application to implement a tunable Gm-C filter is presented. The linearity of the OTA is improved by attenuation and source degeneration techniques. The attenuation technique is implemented by bulk driven cell which is used for low supply voltage circuits. The OTA is designed to operate with a 0.9 V supply voltage and consumes 58.8 μW power. A 600 mVppd sine wave input signal at 1 MHz frequency shows total harmonic distortion (THD) better than -40 dB over the tuning range of the transconductance. The OTA has been used to realize a tunable Gm-C low-pass filter with gain tuning from 5 dB to 21 dB with 4 dB gain steps, which results in power consumptions of 411.6 to 646.8 μW. This low voltage filter can operate as channel select filter and variable gain amplifier (VGA) for wireless sensor network (WSN) applications. The proposed OTA and filter have been simulated in 0.18 μm CMOS technology. Corner case and temperature simulation results are also included to forecast process and temperature variation affects after fabrication.

An important characteristic of second breakdown in p-n junctions is the current constriction to a small region. This may be caused by a thermal feedback mechanism, as discussed by Scarlett and Shockley, and by Bergmann and Gerstner. A brief review of this theory is given, illustrated by experimental results of a simple model arrangement consisting of three thermally coupled transistors. The essential parameters influencing the thermal stability of the current distribution are device geometry, power density, and temperature dependence of current. It is widely known that second breakdown occurs at high voltages at a much lower power level than at low voltages. To allow a more detailed discussion of this effect in view of thermal stability, we determined experimentally the temperature coefficient of transistor current for various Si planar transistors as a function of current, voltage, and junction temperature. The experimental procedure is described and the results are discussed. The experimental values of the temperature coefficient range from 0.08 to 0.01 1/°C. The values for high currents are much lower than predicted by the theory of Ebers and Moll. It thus can easily be understood why, in the case of high current, and low voltage, the thermal stability of the current distribution is much better than in the case of low current and high voltage.

Traditional bandgap-based current references display various limitations. This includes large temperature coefficients (TCs) across process corners, necessitating costly trimming cycles, and area inefficiency for low current values (<10 μA). This work addresses these shortcomings by generating a complementary to absolute temperature (CTAT) current that reproduces the temperature dependence of the proportional to absolute temperature (PTAT) current including its curvature over process corners, eliminating multi-temperature TC trimming while retaining a single-point room-temperature calibration to set the absolute current. The design provides this matching PTAT/CTAT feature by relying on the temperature-stable negative TC of the electron mobility to generate the CTAT current instead of the nonlinear and process-sensitive diode-based CTAT generation. Moreover, thanks to the mobility-based CTAT generation, high-resistivity undoped poly resistors with a strong negative TC can be used, enabling area-efficient CTAT current generation in the sub-μA to single-digit μA range. To validate the proposed approach, we fabricated a prototype design in a 130nm SOI CMOS technology, occupying an active area of only 0.016 mm2 and operating over a wide supply range from 1.6V to 3V. Measurements from 10 chips yield a mean current of 1.1 μA (σ/μ ≈ 4.4%) close to the design target of 1.2 μA. Experimental results further demonstrate an average TC of 110 ppm/∘C from 0 ∘C to 100 ∘C without multi-temperature trimming, an average room-temperature supply line sensitivity of 1000 ppm/V, and a load sensitivity better than 250 ppm/V.

This paper presents a low-power, low-voltage, and low-temperature-coefficient (TC) MOSFET-only subthreshold voltage reference circuit based on a standard 0.18-μm n-well CMOS process. The circuit consists of two novel current generators and an I/V conversion circuit with temperature compensation. Under the control of a proposed pMOS-bulk-driven (PBD) temperature compensation circuit, two pMOSFETs operating in a linear region act as resistors with different TCs and can be used for PTAT and CTAT current generation. Owing to the PBD technique and the subthreshold operating method, these two current generators and the I/V conversion circuit can operate at low voltage. The proposed reference circuit is realized with only standard V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> (SVT) MOS devices. The measurement results show that it can operate at a minimum supply voltage of 0.5 V. The line sensitivity is 0.09% for supply voltages between 0.5 and 1.8 V. The PSRR measured at 100 Hz is 51.8 dB. A measurement of 20 samples indicates that the average TC is 35.7 ppm/°C across a temperature range of -40 to 85 °C. The proposed circuit consumes 17.6 nW from a 0.5-V power supply and occupies an active area of 0.0092 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Metal-oxide based bipolar Resistive RAM (RRAM) is one of the most promising candidates for the future non-volatile data storage. Due to unique properties e.g., small footprint, ability to modulate resistance states in wide ranges dynamically, hysteresis and CMOS compatibility, RRAM can be a fruitful candidate for analog circuit design. However, the recent literature only scratches the surface of this interesting prospect. In this paper, a single RRAM behavior is studied under temperature, voltage and process variations from an analog design standpoint. A comparative study is performed between two analog circuits namely, Common Source (CS) amplifier and differential amplifier with traditional passive resistors and with passive resistors replaced by RRAM along with two other design examples, namely constant <inline-formula><tex-math notation="LaTeX">$g_m$</tex-math></inline-formula> biasing circuit and active low-pass filter, where RRAM can be integrated into analog circuits. Our study shows that blind swapping of passive resistors with RRAM in analog circuits can actually degrade the performance metrics. We propose techniques such as usage of RRAM Low Resistance State (LRS) to recover the loss. We also note that hyperbolic I-V characteristics of RRAM can inherently improve the linearity of RRAM based analog designs. Simulation results indicate that RRAM based amplifiers can achieve 2X area reduction, about 1.5X higher bandwidth with only <inline-formula><tex-math notation="LaTeX">$\approx 9\%$</tex-math></inline-formula> reduction in gain. The resistance modulation property of RRAM is applied to realize a source degenerated amplifier with reconfigurable linearity, to a constant transconductance bias circuit to avoid resistance trimming and to design a programmable active low pass filter.

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 /spl mu/m mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20/spl deg/C to +100/spl deg/C and a supply voltage range of 1.4 V to 3 V with /spl plusmn/30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners.

New digital reference current generation for shunt active power filter under distorted voltage conditions