A new low voltage precision CMOS current reference with no external components

Ultra-low-power (ULP) sensor technologies for the future internet of things have presented challenges in ULP implementation of reference circuits while keeping traditional requirements of stable performance. For voltage reference circuits, as an essential block in SoCs to generate various internal supply voltages, the bandgap voltage-reference (BGVR) scheme has been widely used since it provides a well-defined value with strong immunity to process/voltage/temperature variations. Nanowatt-consuming BGVR circuits have been recently proposed using a capacitor network [4] and a leakage-based proportional-to-absolute-temperature (PTAT) circuit [5]. On the other hand, the current reference circuit that is required to set internal bias current still presents difficulties in achieving both stable performance and ULP consumption. The general approach to building a current reference is to use a BGVR with additional resistors for V-to-I conversion. Though it can provide a well-defined stable current reference, it also requires excessively large resistance for ULP consumption. Another approach is a CMOS-based current reference circuit that tries to make the exponential term in the subthreshold current equation constant or temperature-independent, hence reducing process and temperature dependencies. While CMOS reference circuits have achieved ULP implementations, the current is still determined by a number of process and design parameters, resulting in large sensitivity to process variations. This paper presents a sub-10nW bandgap-reference (BGR) circuit that implements both voltage and current references in one circuit. The BGR circuit is implemented with a 0.18µm CMOS process and generates voltage and a current references of 1.238V and 6.64nA while consuming 9.3nW. The voltage and current references show standard deviations of 0.43% and 1.19% with temperature coefficients of 26ppm/°C and 283ppm/°C, respectively.

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35 µm CMOS process demonstrate that a temperature coefficient of 10.2 ppm/°C is realised with temperature ranging from −40°C to 140°C, and a power supply rejection ratio of 58 dB is achieved with a maximum supply current of 27 µA. The active area of the presented BGR is 160 × 140 µm2.

A novel high-order curvature-compensated CMOS bandgap voltage reference (BGR) is proposed in CSMC 0.5μm CMOS process. By adding a piecewise-curvature current in the low temperature region and a piecewise-curvature current in the high temperature region to a conventional BGR, the proposed high-order curvature-compensated BGR achieves a reference voltage with lower temperature coefficient (TC). Simulation results show that the TC of the proposed high-order curvature-compensated BGR is only 0.62ppm/°C while the TC of the conventional BGR is about 2.82ppm/°C. The proposed high-order curvature-compensated BGR achieves the power supply rejection ratio (PSRR) of −53.98dB, −53.97dB, −52.84dB, −39.097dB and −21.75dB at 10Hz, 1kHz, 10kHz, 100kHz and 1MHz respectively.

Based on the 180 nm CMOS process, a high-precision current mode bandgap reference with ultra-low temperature drift coefficient was designed. The temperature coefficient of the current mode bandgap reference is analyzed, and a current mode curvature correction technology based on the parabolic current correction architecture is proposed to correct the temperature drift coefficient of the output voltage of the current mode bandgap reference, and the curvature compensation module uses only 6 MOS transistors, which consumes less than 200 nA current, and optimizes the temperature coefficient of the bandgap reference output voltage by 96%. The circuit does not use any trimming techniques, which reduces the chip area, reduces the cost of chip mass production, and greatly reduces the temperature drift coefficient over a wide temperature range. The supply voltage is in the range of $1.2 \mathrm{~V}-2.5 \mathrm{~V}$, the bandgap reference has a stable output of 0.6 V, a linear regulation of 0.2%, and a temperature drift coefficient of only $0.303 \times 10^{-6} /{ }^{\circ} \mathrm{C}$ in the range of $-40^{\circ} \mathrm{C}-125^{\circ} \mathrm{C}$. At an ambient temperature of $27^{\circ} \mathrm{C}$, the quiescent current is 50.4 uA, and the chip area is $0.3 \mathrm{~mm} \times 0.1 \mathrm{~mm}$.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

ABSTRACTA bulk-isolated curvature-compensated bandgap voltage reference (BGR) compatible with triple-well CMOS technologies is presented in this paper. Verification results of the proposed BGR implemented in a 0.35-µm 3.3-V triple-well CMOS technology demonstrate that the BGR achieves a reference voltage of 220.4 mV with an average temperature coefficient (TC) of 3.7 ppm/°C in the −40 to 130°C range with 8-bit trimming. The measured current consumption and power supply rejection of the circuit are 33.15 µA and −69.51 dB at 100 Hz, respectively (VDD = 3.3 V). The circuit is capable of operating with supply voltages down to 2 V and its line regulation is 0.16%/V over a voltage range from 2 to 3.6 V. The root mean square output noise voltage in the 0.1–10 Hz frequency range is 2.54 µV. Moreover, measurement results show that the substrate noise sensitivity at the BGR output improved more than 30 dB for frequencies up to 50 kHz, thanks to the employed block bulk isolation strategy, although the effective improvement is expected to be more than 75 dB without the coupling from the electrostatic discharge diode in the I/O pad.

This paper presents a high wide band power supply rejection ratio (PSRR) current mode bandgap reference (BGR) with a fast startup performance. The BGR includes three main enhancement techniques to improve the PSRR. The proposed design is implemented in 130nm CMOS technology. It only consumes 50μA from a 1.8V supply. The BGR provides 850mV reference voltage and has a power supply rejection ratio (PSRR) of 130dB from DC to 100Hz and more than 110dB till 100MHz. The temperature coefficient (TC) is 10 ppm/°C from -40°C to 125° C. The Bandgap start-up time is 70ns.

This paper presents a temperature-compensated CMOS current reference with low line regulation current mirror. The circuit is based on a bandgap reference voltage that achieves the temperature compensation of resistor by the negative temperature coefficient (TC) of a high-resistance polysilicon (HR poly) resistor with the positive TC of an n-well resistor. The low line regulation current mirror is implemented by using a negative feedback connected operational amplifier. Prototypes of 1 μA current reference from 0.35 μm CMOS process show a maximum temperature coefficient of 139 ppm/°C for a temperature range of 0---80 °C. The line regulation is reduced to 0.5 %/V for supply voltage of 3.5 to 5.5 V.

A new 1-V high precision second-order compensated bandgap voltage reference (BGR) is presented in this paper. It utilizes a conventional first-order current-mode BGR to balance the Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT with a Proportional to Absolute Temperature (PTAT) voltage. The residual second-order error is corrected by the difference of two CTAT voltages with different non-linear terms through control of the collector currents of BJTs. All the circuits are designed using a standard 0.18μm CMOS process. The post-simulation results show that the maximum temperature coefficient (TC) of the proposed BGR at 1 V power supply is 2.5 ppm/°C over temperature range of −40 °C to 125 °C. The line regulation is 0.23 mV/V over supply range of 0.9 V–2 V. The low frequency power supply rejection of the circuit is −53 dB at 1 V power supply.

This work presents a 0.4-V supply, 12-nW reverse bandgap voltage reference (BGR) with single BJT and indirect curvature compensation. To achieve sub-0.5V operation, the proposed BGR employs the reverse BGR based complementary-to-absolute-temperature (CTAT) voltage generator, which does not suffer from the settling error and thus reducing the biasing current for the BJT. The reduction in BJT biasing current can reduce the power consumption, thus relieving the burden on the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> charge pump as well, in which the minimum supply voltage of the proposed BGR decreases down to 0.4 V. In this paper, we employ a differential pair proportional-to-absolute-temperature (PTAT) voltage generator to provide a sufficiently large PTAT voltage. To suppress the temperature coefficient (TC) under limited power and voltage budgets, we propose using a nA level PTAT plus nonlinear current to bias both the BJT and PTAT voltage generator. This approach provides an indirect voltage curvature compensation. The proposed reverse BGR fabricated in 65 nm CMOS, occupies an active area of 0.0470 mm2. Measurement results from 8 chips show an average reference voltage of 487.4 mV under 0.4 V supply, with an average TC of 28.4 ppm/°C over a temperature range from -40°C to 100°C, while consuming only 12 nW power.

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

Design analysis of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies and structures are discussed in this paper. Some wide temperature range bandgap voltage reference circuits are included and analysed. Several solutions for total bandgap voltage reference error minimization are proposed. A proposed bandgap voltage reference with output voltage accuracy 1.2V plusmn 0.35% over the temperature range of -40 to 125degC

Bandgap references (BGRs) are widely used to generate a temperature-insensitive reference voltage determined by the silicon bandgap. the BGR generally utilizes PN diodes to generate both of proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption [1], BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD/(n·VT)</sup> to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.

In this paper, a novel CMOS bandgap reference (BGR) with high-order curvature compensation by employing only a MOS transistor operating in strong-inversion deep-triode region is proposed. The mechanism of the compensation technique is analyzed in detail and the BGR is designed in standard 65-nm CMOS process. The simulation results show that the presented BGR achieves a temperature coefficient (TC) of 9.8 ppm/°C over the temperature range of -20°C to 150°C at 2.5V supply voltage. And a high precision reference voltage of 1.2V is obtained under room temperature (27°C). The line regulation is 0.33%/V in the supply voltage ranging from 1.8 to 3.6V. Comparing with the conventional circuit, the proposed architecture improves the accuracy over temperature and saves the chip area effectively.

In order to meet the market demand for wide temperature range and high precision bandgap voltage reference, this paper designs a bandgap reference with wide temperature range and low temperature coefficient. In this paper, the basic implementation principle of the bandgap reference is analyzed.On the basis of the traditional bandgap reference circuit structure,this design adds a trimming network and a temperature compensation network. A new Gaussian bell curve compensation technique is adopted to compensate the low temperature section, and the normal temperature section and the high temperature section respectively. Compared with the existing compensation technology, the versatility and the compensation effect is better. The designed circuit is designed and manufactured based on the Huahong HHNECGE0.35um process. The results show that the output voltage is 2.5V at 2.7V supply voltage and temperature range of -40-125°C.at typical process angle ,the temperature coefficient is 0.54618 PPm/°C,and is within 1PPm/°C at other process angles.