A high precision bandgap voltage reference

A novel high-order curvature-compensated CMOS bandgap voltage reference (BGR) is proposed in CSMC 0.5μm CMOS process. By adding a piecewise-curvature current in the low temperature region and a piecewise-curvature current in the high temperature region to a conventional BGR, the proposed high-order curvature-compensated BGR achieves a reference voltage with lower temperature coefficient (TC). Simulation results show that the TC of the proposed high-order curvature-compensated BGR is only 0.62ppm/°C while the TC of the conventional BGR is about 2.82ppm/°C. The proposed high-order curvature-compensated BGR achieves the power supply rejection ratio (PSRR) of −53.98dB, −53.97dB, −52.84dB, −39.097dB and −21.75dB at 10Hz, 1kHz, 10kHz, 100kHz and 1MHz respectively.

A novel bandgap reference (BGR) with low temperature and supply voltage sensitivity without any resistor, which is compatible with standard CMOS process, is presented in this article. The proposed BGR utilises a differential amplifier with an offset voltage proportional to absolute temperature to compensate the temperature drift of emitter–base voltage. Besides, a self-biased current source with feedback is used to provide the bias current of the BGR core for reducing current mirror errors dependent on supply voltage and temperature further. Verification results of the proposed BGR implemented with 0.35 µm CMOS process demonstrate that a temperature coefficient of 10.2 ppm/°C is realised with temperature ranging from −40°C to 140°C, and a power supply rejection ratio of 58 dB is achieved with a maximum supply current of 27 µA. The active area of the presented BGR is 160 × 140 µm2.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

This article presents a low-power bandgap reference (BGR) featuring high power supply rejection ratio (PSRR) and fast start-up capability, operating across a wide supply voltage range of 1.3–5 V. A novel prebiased pulse current injection technique is proposed in the start-up circuit, achieving a 1% settling time of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$50~\mu $</tex-math> </inline-formula>s and a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$25\times $</tex-math> </inline-formula> speed gain during start-up. To enhance supply noise immunity, the proposed BGR employs a preregulated (PR)-based amplifier that effectively decouples the reference voltage from supply voltage fluctuations. Fabricated in a 0.18-<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $</tex-math> </inline-formula>m BCD process, the proposed reference occupies an active area of 0.0394 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>. Under a 5 V supply, the circuit generates a 1.2 V reference voltage while consuming only 48 nA quiescent current. Operating down to a minimum supply voltage of 1.3 V, it maintains a low power consumption of 57.2 nW at room temperature. The reference exhibits an average temperature coefficient (TC) of 5.95 ppm/°C across a wide temperature range (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 40~^{\circ }$</tex-math> </inline-formula>C to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$125~^{\circ }$</tex-math> </inline-formula>C) and achieves an outstanding line sensitivity (LS) of 0.00308%/V over the 1.3–5 V supply range. Furthermore, the measured PSRR reaches −85 dB at 100 Hz.

This paper presents a high-precision, low temperature coefficient (TC) CMOS bandgap reference for high-performance multi-channel ADC working under wide temperature range. A piecewise curvature compensation technique is proposed to extend its operating temperature range and keep its low temperature coefficient. A s-compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of β in the BJTs. Moreover, the trimming resistors are implemented to calibrate the 1st-order temperature coefficient and absolute value of the output voltage. The bandgap reference designed in 0.18μm CMOS process has a super low temperature coefficient of 2.1ppm/°C over a wide temperature of −55 ° C to 140 ° C, making it appropriate to provide reference voltage for a high-precision ADC.

Based on the 180 nm CMOS process, a high-precision current mode bandgap reference with ultra-low temperature drift coefficient was designed. The temperature coefficient of the current mode bandgap reference is analyzed, and a current mode curvature correction technology based on the parabolic current correction architecture is proposed to correct the temperature drift coefficient of the output voltage of the current mode bandgap reference, and the curvature compensation module uses only 6 MOS transistors, which consumes less than 200 nA current, and optimizes the temperature coefficient of the bandgap reference output voltage by 96%. The circuit does not use any trimming techniques, which reduces the chip area, reduces the cost of chip mass production, and greatly reduces the temperature drift coefficient over a wide temperature range. The supply voltage is in the range of $1.2 \mathrm{~V}-2.5 \mathrm{~V}$, the bandgap reference has a stable output of 0.6 V, a linear regulation of 0.2%, and a temperature drift coefficient of only $0.303 \times 10^{-6} /{ }^{\circ} \mathrm{C}$ in the range of $-40^{\circ} \mathrm{C}-125^{\circ} \mathrm{C}$. At an ambient temperature of $27^{\circ} \mathrm{C}$, the quiescent current is 50.4 uA, and the chip area is $0.3 \mathrm{~mm} \times 0.1 \mathrm{~mm}$.

This paper has presented a structure for bandgap reference with wide operating range of temperature by adopting high precision subtractor to eliminate the non-linearization of the TC(temperature coefficient) of V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BE</inf> . Firstly with the adoption of the technique of curvature compensation, a current with zero TC is obtained. Upon this with the use of subtractor the linear ized V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BE</inf> is achieved. Furthermore, a mixed topology for the output is adopted to add the linearized V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BE</inf> to the PTAT (proportional to abstract temperature) voltage so as to obtain an adjustable output voltage. This bandgap based on the process of 0.6µm BiCMOS demonstrates a TC (temperature coefficient) of 4.21ppm/° within the temperature of −50∼140° with the supply voltage of 3.3V and the output voltage of 1V.

A formalized technique for the automated design of bandgap voltage reference (BVR) is proposed. The distinctive feature of the technique is the automation of the synthesis of the circuit engineering conceptions by the given parameters of the source, which considerably reduces the design time. Based on the developed technique by the 180-nm SOI technology, the circuit of the voltage reference source was designed. The obtained schematic solution has the following desired characteristics: the power supply suppression ratio at the frequencies of 1 kHz in the worst case is –60 dB and at the frequencies of 1 MHz is –44 dB, the maximum consumption current is 25 μA, the temperature coefficient is 24 ppm/°C in the temperature range from –70 to 150°C, and the ratio of changing the output voltage to changing the supply voltage is 354 μV/V in the range of supply voltage from 2.4 to 7 V.

A high-order curvature-compensated CMOS bandgap reference (BGR) topology with a low temperature coefficient (TC) over a wide temperature range and a high power supply reject ratio (PSRR) is presented. High-order correction is realized by incorporating a nonlinear current INL, which is generated by ∆VGS across resistor into current generated by a conventional first-order current-mode BGR circuit. In order to achieve a high PSRR over a broad frequency range, a voltage pre-regulating technique is applied. The circuit was implemented in CSMC 0.5 μm 600 V BCD process. The experimental results indicate that the proposed topology achieves TC of 0.19 ppm/°C over the temperature range of 165 °C (−40 to 125 °C), PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, it achieves a line regulation performance of 0.017%/V in the supply range of 2.8–20 V.

ABSTRACTA bulk-isolated curvature-compensated bandgap voltage reference (BGR) compatible with triple-well CMOS technologies is presented in this paper. Verification results of the proposed BGR implemented in a 0.35-µm 3.3-V triple-well CMOS technology demonstrate that the BGR achieves a reference voltage of 220.4 mV with an average temperature coefficient (TC) of 3.7 ppm/°C in the −40 to 130°C range with 8-bit trimming. The measured current consumption and power supply rejection of the circuit are 33.15 µA and −69.51 dB at 100 Hz, respectively (VDD = 3.3 V). The circuit is capable of operating with supply voltages down to 2 V and its line regulation is 0.16%/V over a voltage range from 2 to 3.6 V. The root mean square output noise voltage in the 0.1–10 Hz frequency range is 2.54 µV. Moreover, measurement results show that the substrate noise sensitivity at the BGR output improved more than 30 dB for frequencies up to 50 kHz, thanks to the employed block bulk isolation strategy, although the effective improvement is expected to be more than 75 dB without the coupling from the electrostatic discharge diode in the I/O pad.

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 /spl mu/m mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20/spl deg/C to +100/spl deg/C and a supply voltage range of 1.4 V to 3 V with /spl plusmn/30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners.

The design of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies is discussed in this paper. Several solutions of total bandgap voltage reference error minimization are considered. As a summary it is proposed bandgap voltage reference with output voltage accuracy 1.2V ± 0.08% in temperature range -40...125°C.

Based on the negative temperature characteristics of threshold voltage and positive temperature characteristics of a multiple of thermal voltage, adding them with proper weight coefficient A voltage reference circuit was proposed with a zero temperature coefficient (TC). The device consists of pure MOSFET operated in subthreshold region and uses no resistors and bipolar transistors. The triple-branch current reference structure is adopted for independence of supply voltage instead of cascade structure and embedded operational amplifier structure with the merit of chip area and power consumption. Simulation results showed that based on standard CMOS 0.18 um process, the circuit can operate at 0.75 V supply voltage with the output voltage only 563 mV. The TC of the voltage was 17.5 ppm/℃ in a range from −40 ℃–125 ℃. The line sensitivity was 569.5 ppm/V in a supply voltage range of 1.2 V–1.8 V, and the power supply rejection ratio (PSRR) was 66.5 dB at 100 Hz. The power dissipation was only 187.4 nW.

A high precision band-gap reference (BGR) with piecewise-linear compensation is designed in this paper. A low voltage Brokaw BGR architecture is employed to provide low output voltage. A high gain, low power supply rejection ratio (PSRR) operational amplifier is designed to improve the PSRR of the band-gap reference. In order to achieve temperature stability significantly lower than the traditional band-gap reference, a circuit which produces a current with positive temperature coefficient (TC) at high temperatures and 0 current at lower temperatures is designed. The whole BGR circuits are simulated by Spectre based on chartered 0.18μm 1P5M 1.8V CMOS technology. It's clear from simulation result that the TC of the output reference voltage approaches 2.61ppm/K over the military temperature range, the PSRR reaches 107.2dB at low frequency (f=0.1HZ), the whole BGR dissipates 0.4mW. In addition, the output reference voltage changes only 8.6μV when the power supply changes from 1.5V to 2.1V, that is to say, the power regulation ratio is 0.014mV/V.

In this paper, A precision bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low-temperature coefficient (TC) is designed. It comprises a bandgap reference core circuit, a negative feedback loop, a nonlinear temperature compensation circuit, and a bias circuit. The bias circuit is used to increase the PSRR, a negative feedback loop is introduced to maintain the constant output reference voltage, and a nonlinear compensation circuit is used to increase the temperature drift coefficient of the bandgap reference. The voltage supply is 3. 3V. This simulation is based on the SMIC 0.1S$\mu$m CMOS process. The results show that the temperature drift coefficient of the bandgap reference source is 3.255ppm/°C in the temperature range of −40°C~130°C. The PSRR is 103. 192dB at the frequency of 1Hz. The power consumption is 13.1996$\mu$W. The offset voltage is 2.15591mV by Monte Carlo simulation.