A resistorless CMOS bandgap reference with low temperature coefficient and high PSRR

A novel high-order curvature-compensated CMOS bandgap voltage reference (BGR) is proposed in CSMC 0.5μm CMOS process. By adding a piecewise-curvature current in the low temperature region and a piecewise-curvature current in the high temperature region to a conventional BGR, the proposed high-order curvature-compensated BGR achieves a reference voltage with lower temperature coefficient (TC). Simulation results show that the TC of the proposed high-order curvature-compensated BGR is only 0.62ppm/°C while the TC of the conventional BGR is about 2.82ppm/°C. The proposed high-order curvature-compensated BGR achieves the power supply rejection ratio (PSRR) of −53.98dB, −53.97dB, −52.84dB, −39.097dB and −21.75dB at 10Hz, 1kHz, 10kHz, 100kHz and 1MHz respectively.

In order to meet the market demand for wide temperature range and high precision bandgap voltage reference, this paper designs a bandgap reference with wide temperature range and low temperature coefficient. In this paper, the basic implementation principle of the bandgap reference is analyzed.On the basis of the traditional bandgap reference circuit structure,this design adds a trimming network and a temperature compensation network. A new Gaussian bell curve compensation technique is adopted to compensate the low temperature section, and the normal temperature section and the high temperature section respectively. Compared with the existing compensation technology, the versatility and the compensation effect is better. The designed circuit is designed and manufactured based on the Huahong HHNECGE0.35um process. The results show that the output voltage is 2.5V at 2.7V supply voltage and temperature range of -40-125°C.at typical process angle ,the temperature coefficient is 0.54618 PPm/°C,and is within 1PPm/°C at other process angles.

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 /spl mu/m mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20/spl deg/C to +100/spl deg/C and a supply voltage range of 1.4 V to 3 V with /spl plusmn/30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

In this paper, A precision bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low-temperature coefficient (TC) is designed. It comprises a bandgap reference core circuit, a negative feedback loop, a nonlinear temperature compensation circuit, and a bias circuit. The bias circuit is used to increase the PSRR, a negative feedback loop is introduced to maintain the constant output reference voltage, and a nonlinear compensation circuit is used to increase the temperature drift coefficient of the bandgap reference. The voltage supply is 3. 3V. This simulation is based on the SMIC 0.1S$\mu$m CMOS process. The results show that the temperature drift coefficient of the bandgap reference source is 3.255ppm/°C in the temperature range of −40°C~130°C. The PSRR is 103. 192dB at the frequency of 1Hz. The power consumption is 13.1996$\mu$W. The offset voltage is 2.15591mV by Monte Carlo simulation.

In this paper, a novel CMOS bandgap reference (BGR) with high-order curvature compensation by employing only a MOS transistor operating in strong-inversion deep-triode region is proposed. The mechanism of the compensation technique is analyzed in detail and the BGR is designed in standard 65-nm CMOS process. The simulation results show that the presented BGR achieves a temperature coefficient (TC) of 9.8 ppm/°C over the temperature range of -20°C to 150°C at 2.5V supply voltage. And a high precision reference voltage of 1.2V is obtained under room temperature (27°C). The line regulation is 0.33%/V in the supply voltage ranging from 1.8 to 3.6V. Comparing with the conventional circuit, the proposed architecture improves the accuracy over temperature and saves the chip area effectively.

ABSTRACTA bulk-isolated curvature-compensated bandgap voltage reference (BGR) compatible with triple-well CMOS technologies is presented in this paper. Verification results of the proposed BGR implemented in a 0.35-µm 3.3-V triple-well CMOS technology demonstrate that the BGR achieves a reference voltage of 220.4 mV with an average temperature coefficient (TC) of 3.7 ppm/°C in the −40 to 130°C range with 8-bit trimming. The measured current consumption and power supply rejection of the circuit are 33.15 µA and −69.51 dB at 100 Hz, respectively (VDD = 3.3 V). The circuit is capable of operating with supply voltages down to 2 V and its line regulation is 0.16%/V over a voltage range from 2 to 3.6 V. The root mean square output noise voltage in the 0.1–10 Hz frequency range is 2.54 µV. Moreover, measurement results show that the substrate noise sensitivity at the BGR output improved more than 30 dB for frequencies up to 50 kHz, thanks to the employed block bulk isolation strategy, although the effective improvement is expected to be more than 75 dB without the coupling from the electrostatic discharge diode in the I/O pad.

The reference voltage is a core part of RFID tags, its performance directly determines the whole chip's life and performance. The temperature coefficient is one of the important performances of the reference voltage source and the high-order temperature compensation is an effective method to reduce the temperature coefficient of the reference source. A low temperature coefficient bandgap reference is designed based on the standard 65nm CMOS process, and the low-supply voltage operation with bandgap reference circuit with current mode structure. The designed CMOS bandgap voltage reference is in the range of -20°C to 100°C with temperature coefficient of 9.6 ppm/°C and provides a good Power Supply Rejection Ratio(PSRR) of 79dB in the low frequency. The results of simulation show that the design improve the performance of the bandgap reference voltage source effectively.

In this paper, an all CMOS current reference circuit which generates a reference current independent of PVT (Process, supply Voltage, and Temperature) variations is presented. The circuit consists of a self-biased current source (SBCS) and two nested connected transistors which supply a voltage with positive temperature coefficient and the resulting reference circuit has low temperature coefficient. It is based on CSMC 0.5um mixed-signal process with the supply voltage of 5V. The precision of reference current is about ±3.05% when considering the process, supply voltage and temperature variation at the same time.

The design of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies is discussed in this paper. Several solutions of total bandgap voltage reference error minimization are considered. As a summary it is proposed bandgap voltage reference with output voltage accuracy 1.2V ± 0.08% in temperature range -40...125°C.

This paper presents a high-precision, low temperature coefficient (TC) CMOS bandgap reference for high-performance multi-channel ADC working under wide temperature range. A piecewise curvature compensation technique is proposed to extend its operating temperature range and keep its low temperature coefficient. A s-compensation technique is used to cancel the PTAT and non-PTAT spread of the output due to variation of β in the BJTs. Moreover, the trimming resistors are implemented to calibrate the 1st-order temperature coefficient and absolute value of the output voltage. The bandgap reference designed in 0.18μm CMOS process has a super low temperature coefficient of 2.1ppm/°C over a wide temperature of −55 ° C to 140 ° C, making it appropriate to provide reference voltage for a high-precision ADC.

Bandgap reference (BGR) circuits are widely used due to their stable output voltage over process, supply voltage and temperature variations. Reference voltage stability is critical for data-acquisition applications and lower supply voltages can reduce the power of mixed-signal systems. However BGR for analog circuits is one of the bottlenecks for sub-1V supply operation because BGR supply voltage is limited by V EB +V DS [1]. V EB refers to the emitter-base voltage of a pnp transistor which is limited to ~0.6 to 0.7V due to silicon junction cut-in voltage, while V DS is the drain-source saturation voltage of a current-mirror. The BGR temperature dependence is decided by the weighted sum of proportional-to-absolute-temperature(PTAT) and complementary-to-absolute-temperature (CTAT) terms. An alternative PTAT generator can be implemented by dV GS (gate-to-source voltage difference) of a MOS pair in subthreshold [2]. The CTAT generator can be implemented by special devices or using the gate-source voltage V GS of subthreshold MOSFETs. Although the V GS of a subthreshold MOSFET is smaller than emitter-base voltage of a pnp transistor, the MOSFET model inaccuracy in the subthreshold region and high process-dependent characteristic of MOSFET gate-source voltage induces high variation for voltage reference circuits.

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

A band-gap voltage reference applicable for LDO circuit was designed. The band-gap voltage reference with lower change rate and low temperature-drift and high PSRR was acquired, which uses the two stage operational amplifier as the input terminal, and the miller compensation circuit was adopted in order to improve the stability of the voltage reference circuit. The circuit was simulated with Cadence tool and 0.5μm CMOS model. The results show that the reference voltage is 1.2182V, the PSRR of band-gap voltage reference is-76.8dB. The measured results indicated that the designed band-gap voltage reference is prospective for application in LDO circuit.

Based on the 180 nm CMOS process, a high-precision current mode bandgap reference with ultra-low temperature drift coefficient was designed. The temperature coefficient of the current mode bandgap reference is analyzed, and a current mode curvature correction technology based on the parabolic current correction architecture is proposed to correct the temperature drift coefficient of the output voltage of the current mode bandgap reference, and the curvature compensation module uses only 6 MOS transistors, which consumes less than 200 nA current, and optimizes the temperature coefficient of the bandgap reference output voltage by 96%. The circuit does not use any trimming techniques, which reduces the chip area, reduces the cost of chip mass production, and greatly reduces the temperature drift coefficient over a wide temperature range. The supply voltage is in the range of $1.2 \mathrm{~V}-2.5 \mathrm{~V}$, the bandgap reference has a stable output of 0.6 V, a linear regulation of 0.2%, and a temperature drift coefficient of only $0.303 \times 10^{-6} /{ }^{\circ} \mathrm{C}$ in the range of $-40^{\circ} \mathrm{C}-125^{\circ} \mathrm{C}$. At an ambient temperature of $27^{\circ} \mathrm{C}$, the quiescent current is 50.4 uA, and the chip area is $0.3 \mathrm{~mm} \times 0.1 \mathrm{~mm}$.