Bandgap voltage reference: errors and techniques for their minimization

The design of CMOS bandgap voltage references focusing on high accuracy and low temperature coefficient methodologies is discussed in this paper. Several solutions of total bandgap voltage reference error minimization are considered. As a summary it is proposed bandgap voltage reference with output voltage accuracy 1.2V ± 0.08% in temperature range -40...125°C.

A new PVT compensated voltage reference is presented by using switched-capacitor (S.C.) technique. In the proposed bandgap voltage reference (BGR), a p–n junction is biased with different currents during two different phases and required PTAT and CTAT voltages generated and held by two capacitors. Using a capacitive voltage divider, the PTAT voltage is weighted such that the sub-1V bandgap voltage is achievable. In order to cancel the effect of op-amp offset and to relax the design of op-amp, the offset voltage of the op-amp is sampled by a capacitor during a specified phase and inversely is added to the final bandgap voltage in next phase. The analysis of the proposed S.C. BGR is supplemented by simulation of a 0.5-V BGR with 28[Formula: see text][Formula: see text][Formula: see text]W power consumption in a standard 0.18[Formula: see text][Formula: see text][Formula: see text]m CMOS technology. Simulation results show that the average temperature coefficient of the S.C. BGR is 17[Formula: see text]ppm/∘C and it is robust against the process variations. Applying an arbitrary 100-mV op-amp offset results in a lower than 1.1[Formula: see text]mV deviation in generated reference voltage. Due to the better matching of MIM capacitors in CMOS process (rather than resistors used in conventional BGR) the proposed S.C. bandgap provides good accuracy without any post trimming. Monte–Carlo analysis shows that [Formula: see text]/[Formula: see text] of the generated reference voltage is as low as 0.7%. The sensitivity of the proposed BGR to supply variation is also less than 1%/V.

In this paper, a Bandgap reference (BGR) with high power supply rejection ratio (PSRR) and low temperature coefficient (TC) is presented. On the basis of first-order temperature-compensated BGR, a complementary curvature-compensation technique (CCCT) is realized by using the saturation region current characteristics of PMOS transistors with proportional to absolute temperature (PTAT) bias voltage. Besides, in addition to the effect of cascode structure and the isolation of the current amplifier, the PSRR of proposed BGR is further improved by adopting self-bias power supply with feedback. The presented BGR is implemented in a standard 0.35 μm BCD process. The post-simulation results show that the TC of the BGR is 4.740 ppm/∘C with a 2.50V average output voltage, and the PSRR is up to -78.5dB.

In order to meet the market demand for wide temperature range and high precision bandgap voltage reference, this paper designs a bandgap reference with wide temperature range and low temperature coefficient. In this paper, the basic implementation principle of the bandgap reference is analyzed.On the basis of the traditional bandgap reference circuit structure,this design adds a trimming network and a temperature compensation network. A new Gaussian bell curve compensation technique is adopted to compensate the low temperature section, and the normal temperature section and the high temperature section respectively. Compared with the existing compensation technology, the versatility and the compensation effect is better. The designed circuit is designed and manufactured based on the Huahong HHNECGE0.35um process. The results show that the output voltage is 2.5V at 2.7V supply voltage and temperature range of -40-125°C.at typical process angle ,the temperature coefficient is 0.54618 PPm/°C,and is within 1PPm/°C at other process angles.

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 /spl mu/m mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1% over a temperature range of -20/spl deg/C to +100/spl deg/C and a supply voltage range of 1.4 V to 3 V with /spl plusmn/30% tolerance for all of the used on- chip resistors. The maximum current variation is slightly less than the oxide thickness variation in the process corners.

This work presents a 0.4-V supply, 12-nW reverse bandgap voltage reference (BGR) with single BJT and indirect curvature compensation. To achieve sub-0.5V operation, the proposed BGR employs the reverse BGR based complementary-to-absolute-temperature (CTAT) voltage generator, which does not suffer from the settling error and thus reducing the biasing current for the BJT. The reduction in BJT biasing current can reduce the power consumption, thus relieving the burden on the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> charge pump as well, in which the minimum supply voltage of the proposed BGR decreases down to 0.4 V. In this paper, we employ a differential pair proportional-to-absolute-temperature (PTAT) voltage generator to provide a sufficiently large PTAT voltage. To suppress the temperature coefficient (TC) under limited power and voltage budgets, we propose using a nA level PTAT plus nonlinear current to bias both the BJT and PTAT voltage generator. This approach provides an indirect voltage curvature compensation. The proposed reverse BGR fabricated in 65 nm CMOS, occupies an active area of 0.0470 mm2. Measurement results from 8 chips show an average reference voltage of 487.4 mV under 0.4 V supply, with an average TC of 28.4 ppm/°C over a temperature range from -40°C to 100°C, while consuming only 12 nW power.

This paper presents design of an ultra-high precision bandgap voltage reference circuit in a 180nm BCDMOS 1P6M process. A novel current trimming technique is introduced to achieve high accuracy and low temperature coefficient. This bandgap voltage reference circuit achieves a low 17.1ppm temperature coefficient in measurement and 0.15% 3σ inaccuracy in simulation after trimming at 1.19V over temperature range of −40 to 125°C.

A design of a low voltage bandgap reference (BGR), for SOC application with high accuracy, is described and the chip layout is presented. To compensate the error caused by the current-mirror mismatch, the chopper modulator is used in the BGR to decrease the offset of the opamp. The design features a reference voltage of 0.256V/spl sim/0.768V with supply voltage range from 1 V to 1.5 V and temperature range from -20 /spl deg/C to 60 /spl deg/C. The maximum supply current is 4 /spl mu/A and the area of layout is 0.3 /spl times/ 0.4 mm/sup 2/ with a standard 0.25 /spl mu/m 2P5M n-well CMOS process.

Novel high-PSRR high-order curvature-compensated bandgap voltage reference

Based on the 0.18‐μm BCD process, this paper proposes a novel high‐order bandgap reference. Building on the original concave‐curve bandgap reference, high‐order compensation for the concave‐curve voltage‐mode bandgap reference is realized through β compensation and a piecewise compensation mechanism for source/sink currents. Under a 5‐V supply voltage and an ambient temperature range of −40°C to 125°C, the reference voltage is 1.205 V. The best temperature drift coefficient can reach as low as 0.875 ppm/°C, the power supply rejection ratio is 64.11 dB, the phase margin is 65.6°, the bandwidth can reach 6.2 MHz, and the total power consumption is 60.2 μA. With a power‐on time of 10 μs, the start‐up time of the bandgap reference is only 6.4 μs.

A new 1-V high precision second-order compensated bandgap voltage reference (BGR) is presented in this paper. It utilizes a conventional first-order current-mode BGR to balance the Complementary to Absolute Temperature (CTAT) voltage component of a forward biased BJT with a Proportional to Absolute Temperature (PTAT) voltage. The residual second-order error is corrected by the difference of two CTAT voltages with different non-linear terms through control of the collector currents of BJTs. All the circuits are designed using a standard 0.18μm CMOS process. The post-simulation results show that the maximum temperature coefficient (TC) of the proposed BGR at 1 V power supply is 2.5 ppm/°C over temperature range of −40 °C to 125 °C. The line regulation is 0.23 mV/V over supply range of 0.9 V–2 V. The low frequency power supply rejection of the circuit is −53 dB at 1 V power supply.

This work describes the design steps of a Bandgap Voltage Reference (BGR) with second order curvature compensation to be used in the Space applications. The work focuses on the design of the different sub-circuits which integrate the BGR and the implementation of the trimming sections, to improve the performance in all the special conditions that characterize the target environment. The circuit was designed in a 150 nm Silicon-on-Insulator CMOS technology, using radiation hardening. Simulation results show a performance of 0.758 ppm/°C of temperature coefficient in typical condition over a military temperature range, with a 1.25 V output voltage.

Presently design of a linear and wide range voltage controlled oscillator for analog and mixed mode signal applications with lesser design cycle time is a challenging work for Electronics Engineers. Band Gap reference voltage source is required, since the power supply noise is one of the important factors that affect the PLL noise performance. This paper describes the new design technique of the Band Gap Reference Current Starved Voltage Controlled Oscillator (BG-CSVCO) circuit to reduce power supply noise for PLL application. The BG-CSVCO circuit is designed and simulated using 0.18μm CMOS Technology. The BG-CSVCO has frequency range from 1.59 MHz to 2.87 GHz for the tuning range 0.2V to 1.8V and power consumption is 1.336mW. The supply voltage VDD is 1.8V.

This paper presents a high wide band power supply rejection ratio (PSRR) current mode bandgap reference (BGR) with a fast startup performance. The BGR includes three main enhancement techniques to improve the PSRR. The proposed design is implemented in 130nm CMOS technology. It only consumes 50μA from a 1.8V supply. The BGR provides 850mV reference voltage and has a power supply rejection ratio (PSRR) of 130dB from DC to 100Hz and more than 110dB till 100MHz. The temperature coefficient (TC) is 10 ppm/°C from -40°C to 125° C. The Bandgap start-up time is 70ns.

Bandgap references (BGRs) are widely used to generate a temperature-insensitive reference voltage determined by the silicon bandgap. the BGR generally utilizes PN diodes to generate both of proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) quantities and combines them to eliminate the temperature dependency. Though the BGR provides a robust voltage or current reference with insensitivity to process, voltage and temperature variations that is superior to CMOS-only reference circuits, it has received little attention in ultra-low-power (ULP) sensor applications. While CMOS-only reference circuits have recently demonstrated nanowatt power consumption [1], BGR approaches still have two critical factors to preventing nanowatt consumption. One is that PTAT generation assumes sufficient forward bias, VD, of the PN junction to allow e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VD/(n·VT)</sup> to be much larger than 1 in the temperature range of interest, where n and VT (=kT/q) represent the ideality factor and the thermal voltage, respectively. In addition, the PTAT generation requires a start-up circuit to prevent the circuit from resting at the undesirable zero-bias condition. Since the start-up circuit utilizes a resistive voltage division between power rails, it consumes non-zero DC current, which must be larger than leakage current in order to ensure stable start-up operation. These two requirements for PTAT generation limit the use of BGRs in nanowatt ULP applications.