Quantum Algorithm for Finding the Optimal Variable Ordering for Binary Decision Diagrams

The Sentential Decision Diagram (SDD) is a prominent knowledge representation language that subsumes the Ordered Binary Decision Diagram (OBDD) as a strict subset. Like OBDDs, SDDs have canonical forms and support bottom-up operations for combining SDDs, but they are more succinct than OBDDs. In this paper we introduce an SDD variant, called the Zero-suppressed Sentential Decision Diagram (ZSDD). The key idea of ZSDD is to employ new trimming rules for obtaining a canonical form. As a result, ZSDD subsumes the Zero-suppressed Binary Decision Diagram (ZDD) as a strict subset. ZDDs are known for their effectiveness on representing sparse Boolean functions. Likewise, ZSDDs can be more succinct than SDDs when representing sparse Boolean functions. We propose several polytime bottom-up operations over ZSDDs, and a technique for reducing ZSDD size, while maintaining applicability to important queries. We also specify two distinct upper bounds on ZSDD sizes; one is derived from the treewidth of a CNF and the other from the size of a family of sets. Experiments show that ZSDDs are smaller than SDDs or ZDDs for a standard benchmark dataset.

Ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of BDDs depends on a chosen variable ordering, i.e. the size may vary from linear to exponential, and the problem of improving the variable ordering is known to be NP-complete. In this paper we present a new exact branch & bound technique for determining an optimal variable order. In contrast to all previous approaches, that only considered one lower bound, our method makes use of a combination of three bounds and by this avoids unnecessary computations. The lower bounds are derived by generalization of a lower bound known from VLSI design. They allow to build the BDD either top down or bottom up. Experimental results are given to show the efficiency of our approach.

Optimal ordered binary decision diagrams for read-once formulas

The size of ordered binary decision diagrams (OBDDs) strongly depends on the chosen variable ordering. It is an obvious heuristic to use symmetric variable orderings, i.e., variable orderings where symmetric variables are arranged adjacently. In order to evaluate this heuristic, methods for estimating the OBDD size for random partially symmetric functions are presented. Characterizations of cases where, with high probability, only symmetric variable orderings and, with high probability, only nonsymmetric variable orderings lead to minimum OBDD size are obtained. For this analysis estimates for the number of different blocks of random Boolean matrices are used. © 1998 John Wiley & Sons, Inc. Random Struct. Alg., 13, 49–70, 1998

Specific physical defects of high performance circuits manifest themselves as path delay faults (PDFs). A pair (v1, v2) of test patterns is required to detect a PDF. A PDF is robust testable if there is a test pair on which the fault manifestation does not depend on delays of other circuit paths. A PDF is non robust testable if manifestation of the fault on any test pair is possible only when all other paths of the circuit are fault free. For high quality delay testing it is desirable to detect delay of any path regardless of delays of other paths. In this paper, synthesis of a circuit by covering each nonterminal node of the reduced ordered binary decision diagram (ROBDD) or free binary decision diagram (Free BDD) system with the original subcircuit from gates is suggested. Delay testability of such circuits is investigated. It is specified that the PDF of each path of the circuit is detected without injecting additional inputs into the circuit. It is well known that the BDD is a directed acyclic graph based on the Shannon decomposition in each nonterminal node v: 0 1 i i x x v i v i v f x f x f = = = ∨ . Here fv is the function corresponding to the node v, and the decomposition variable xi marks the node v. The dashed edge drops in the node corresponding to the function 0 i x v f = , and the bold edge drops in the node corresponding to the function 1 i x v f = . The BDD is called ordered (OBDD) if variables are encountered in the same order in all paths connecting the BDD root with the terminal node. The BDD is called reduced (RBDD) if it does not contain either isomorphic subgraphs or nonterminal nodes such that 0 1 i i x x v v f f = = = . An example of reduced and ordered BDD (ROBDD) is shown in Fig. 1. When deriving the Free BDD, a suitable decomposition variable is chosen for each nonterminal node v independently of other nonterminal nodes. That may cut the number of Free BDD of nonterminal nodes in comparison with the ROBDD (for the same function). Let 1 { ,..., } m F f f = be a system of Boolean functions describing combinational circuit behavior. Derive the ROBDD using the same order of variables for each Boolean function from F. Join isomorphic subgraphs in different ROBDDs. Combine different ROBDDs of 1-terminal nodes into one 1-terminal node and their 0-terminal nodes into one 0-terminal node. As a result, we obtain the graph with m roots and two terminal nodes. This graph represents a system of m Boolean functions. It is called the shared ROBDD. Without loss of generality, we will further consider systems with one function as an example. In Fig. 1, the ROBDD for one Boolean function is shown. The ROBDD represents the disjoint sum of products (DSoP) of the function f as follows:

Various versions of binary decision diagrams (BDDs) have been proposed in the past, differing in the reduction rule needed to give meaning to edges skipping levels. The most widely adopted, fully-reduced BDDs and zero-suppressed BDDs, excel at encoding different types of boolean functions (if the function contains subfunctions independent of one or more underlying variables, or it tends to have value zero when one of its arguments is nonzero, respectively). Recently, new classes of BDDs have been proposed that, at the cost of some additional complexity and larger memory requirements per node, exploit both cases. We introduce a new type of BDD that we believe is conceptually simpler, has small memory requirements in terms of node size, tends to result in fewer nodes, and can easily be further extended with additional reduction rules. We present a formal definition, prove canonicity, and provide experimental results to support our efficiency claims.

In this paper, we propose a method for discovering hidden information from large-scale item set data based on the symmetry of items. Symmetry is a fundamental concept in the theory of Boolean functions, and there have been developed fast symmetry checking methods based on BDDs (Binary Decision Diagrams). Here we discuss the property of symmetric items in data mining problems, and describe an efficient algorithm based on ZBDDs (Zero-suppressed BDDs). The experimental results show that our ZBDD-based symmetry checking method is efficiently applicable to the practical size of benchmark databases.

Translation among CNFs, characteristic models and ordered binary decision diagrams

While most of the research efforts on network reliability analysis have focused on networks with imperfect links but perfectly reliable nodes, binary decision diagram–based methods have recently been developed to determine reliability of networks with imperfect links and imperfect nodes. The smaller the binary decision diagram size is, the better the performance of the binary decision diagram–based algorithm will be. The binary decision diagram size heavily depends on the chosen variable ordering. As finding the optimal variable ordering is a nondeterministic polynomial time-complete problem, a heuristic is typically used. Various heuristics based on depth-first search, breadth-first search, and network-driven search have been developed for network reliability analysis. However, they often assume the networks have perfectly reliable nodes. This article advances the state-of-the-art by proposing a new ordering heuristic for the binary decision diagram–based reliability analysis of networks with imperfect links/edges and nodes. Empirical studies show that the proposed new ordering heuristic can generate significantly smaller binary decision diagram size for a wide variety of network structures than the traditional depth-first search–based, breadth-first search–based, network-driven search–based heuristics for most cases, enabling efficient binary decision diagram–based reliability analysis of large-scale networks considering both link and node failures. Robustness of the proposed heuristic is also investigated through empirical studies.

This special issue of the VLSI DESIGN: an International Journal of Custom-Chip Design, Simulation and Testing is devoted to spectral techniques, new types of decision trees and diagrams, their applications, efficient ways of their calculation and mutual relations between spectral techniques and classical decision diagrams. Manipulations and calculations with discrete functions are fundamental tasks in many areas of Computer Science and Engineering. Many problems in digital system design, simulation and testing can be expressed as a sequence of operations on discrete functions. The performance of Computer-Aided Design systems used in solving various problems in this area strongly depends on the efficiency of representations of discrete functions. Decision Diagrams (DDs) have proved very convenient data structure for discrete function representations, permitting manipulations and calculations with large functions efficiently in terms of time and space. In many applications, as for example those involving large matrices, conventional algorithms are significantly improved by using DDs. In logic design, such applications relate to basic problems of the design, verification, simulation and testing logical networks. Besides Boolean functions, some other types of discrete representations, such as multi-valued functions, cube sets, EXOR-based spectral and probabilistic formulas have to be dealt with. Hence the numbers of different decision trees and diagrams have been introduced for these various applications and representations. The spectral or polynomial representation of Boolean function is obtained by expressing it in terms of an orthogonal basis. The most popular basis is formed by discrete Walsh functions. Note that the spectral and the polynomial representation of a Boolean function are equivalent. The discrete orthogonal functions are referred to as the basis functions when the spectral or abstract harmonic terminology is used and as monomials when the polynomial terminology is used. Such polynomial representations have extensive applications in coding theory and cryptography as well as design of nonlinear filters. Spectral techniques based on Walsh, Haar, Arithmetic and Reed–Muller transforms have been used in digital logic design for more than 30 years. These techniques have been used for Boolean function classification, disjoint decomposition, identification of symmetries, parallel and serial linear decomposition, spectral translation synthesis (extraction of linear preand post-filters), multiplexer synthesis, threshold logic synthesis, state assignment and testing, and evaluation of logic complexity. The renewed interest in applications of spectral methods in design of VLSI digital circuits is caused by their excellent design for testability properties and in their efficiency in Boolean mapping problems. Furthermore, the practical applicability of these techniques was greatly improved with the development of efficient methods that allow calculating and operating on spectra of Boolean functions directly from reduced representations of such functions in the form of arrays of cubes or decision diagrams. Following from these recent developments, techniques have been presented for efficient spectral translation to decompose a circuit into a cascade of two sub circuits: linear block composed of EXOR gates fed by the primary input of the overall circuit. Such linear decomposition drastically simplifies the synthesis task. The choice of suitable linear transformation is based on a complexity measure assigned to each Boolean function that is heuristically related to the complexity of the final circuit implementation. To avoid the experimental costs of computing the Walsh transform, Binary Decision Diagrams (BDDs) based techniques are used. Recently the idea of linear transformations is applied to decision diagrams. By combining powerful spectral linear techniques with variable reordering techniques, it is possible to synthesize large Boolean functions with standard Computer-Aided Design tools that fail otherwise. The areas addressed by this special issue span spectral transforms, their applications and efficient calculation methods through decision diagrams. New spectral decision diagrams are also emerging that support larger data structures allowing more complex discrete representations to be implemented that was previously impossible.

The ordered binary decision diagram (OBDD) has proven useful in many applications as an efficient data structure for representing and manipulating Boolean functions. A serious drawback of OBDD's is the need for application-specific heuristic algorithms to order the variables before processing. Further, for many problem instances in logic synthesis, the heuristic ordering algorithms which have been proposed are insufficient to allow OBDD operations to complete within a limited amount of memory. The paper proposes a solution to these problems based on having the OBDD package itself determine and maintain the variable order. This is done by periodically applying a minimization algorithm to reorder the variables of the OBDD to reduce its size. A new OBDD minimization algorithm, called the sifting algorithm, is proposed and appears especially effective in reducing the size of the OBDD. Experiments with dynamic variable ordering on the problem of forming the OBDD's for the primary outputs of a combinational circuit show that many computations complete using dynamic variable ordering when the same computation fails otherwise.

In this paper, we propose a novel symbolic analysis method for analog behavioral modeling by Boolean logic operations and graph representation. The exact symbolic analysis problem is formulated as a logic circuit synthesis problem where we build a logic circuit, which detects whether or not a given symbolic term is a valid product term from a determinant. The logic circuit is represented by binary decision diagrams (BDDs), which can be trivially transformed into zero-suppressed binary decision diagrams (ZBDDs). ZBDDs are essentially determinant decision diagrams (DDDs) representation of a determinant. The significance of the new method is that all product terms can be constructed implicitly and simultaneously, in contrast to all previous symbolic analysis methods where symbolic terms are generated explicitly and sequentially by Laplace expansion or topological methods. We further apply the logic synthesis idea to generating symbolic coefficients of s-expanded polynomials and present a method to compute coefficients individually and selectively. Our new approach demonstrates an inherent relationship between circuit simulation and logic synthesis for the first time. Experimental results show the speedup of our new method over the existing flat method and its greater capacity over both existing flat and hierarchical symbolic analyzers.

The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.

The ordering of variables can have a significant effect on the size of the reduced binary decision diagram (BDD) that represents the set of solutions to a combinatorial optimization problem. It also influences the quality of the objective function bound provided by a limited-width relaxation of the BDD. We investigate these effects for the maximum independent set problem. By identifying variable orderings for the BDD, we show that the width of an exact BDD can be given a theoretical upper bound for certain classes of graphs. In addition, we draw an interesting connection between the Fibonacci numbers and the width of exact BDDs for general graphs. We propose variable ordering heuristics inspired by these results, as well as a k-layer look-ahead heuristic applicable to any problem domain. We find experimentally that orderings that result in smaller exact BDDs have a strong tendency to produce tighter bounds in relaxation BDDs.

Property testing is concerned with deciding whether an object (e.g. a graph or a function) has a certain property or is “far” (for a prespecified distance measure) from every object with that property. In this work we design and analyze an algorithm for testing functions for the property of being computable by a read-once width-2 Ordered Binary Decision Diagram (OBDD), also known as a branching program, where the order of the variables is not known to us. That is, we must accept a function f if there exists an order of the variables according to which a width-2 OBDD can compute f. The query complexity of our algorithm is $\tilde{O}({\rm log n}){\rm poly}(1/\epsilon)$. In previous work (in Proceedings of RANDOM, 2009) we designed an algorithm for testing computability by an OBDD with a fixed order, which is known to the algorithm. Thus, we extend our knowledge concerning testing of functions that are characterized by their computability using simple computation devices and in the process gain some insight concerning these devices.