An efficient variable ordering heuristic for binary decision diagram–based reliability analysis of network with imperfect nodes

In this paper, we propose an algorithm to construct the ordered binary decision diagram (OBDD) representing the cut function of a terminal-pair network. The algorithm recognizes isomorphic sub-problems and thus avoids redundant computations. The system reliability could be efficiently computed by the OBDD. Finally, we propose an approach to compute the importance measures for multiple components by traversing the OBDD only once. The correctness and the effectiveness of our approach are demonstrated by experiments on 30 benchmark networks. The experimental results on a 2-by-100 lattice network, which has 2/sup 99/ paths or 10,000 cuts, show an impressive improvement compared to the previous works using the sum of disjoint products method that have exponential complexity. The CPU time of our method, including the calculation of not only the reliability but also the importance measures, for a 100-stage lattice network is only about 0.24 seconds. Thus, this approach is very helpful for the reliability and sensitivity analysis of large networks.

An ordered binary decision diagram (OBDD) is a directed acyclic graph that represents a Boolean function. Since OBDDs have many nice properties as data structures, they have been extensively studied for decades in both theoretical and practical fields, such as VLSI (Very Large Scale Integration) design, formal verification, machine learning, and combinatorial problems. Arguably, the most crucial problem in using OBDDs is that they may vary exponentially in size depending on their variable ordering (i.e., the order in which the variables are to be read) when they represent the same function. Indeed, it is NP hard to find an optimal variable ordering that minimizes an OBDD for a given function. Friedman and Supowit provided a clever deterministic algorithm with time/space complexity O^∗(3ⁿ), where n is the number of variables of the function, which is much better than the trivial brute-force bound O^∗(n!2ⁿ). This paper shows that a further speedup is possible with quantum computers by presenting a quantum algorithm that produces a minimum OBDD together with the corresponding variable ordering in O^∗(2.77286ⁿ) time and space with an exponentially small error probability. Moreover, this algorithm can be adapted to constructing other minimum decision diagrams such as zero-suppressed BDDs.

Optimal ordered binary decision diagrams for read-once formulas

Efficient Fault Tree Analysis of Complex Fault Tolerant Multiple-Phased Systems

The size of ordered binary decision diagrams (OBDDs) strongly depends on the chosen variable ordering. It is an obvious heuristic to use symmetric variable orderings, i.e., variable orderings where symmetric variables are arranged adjacently. In order to evaluate this heuristic, methods for estimating the OBDD size for random partially symmetric functions are presented. Characterizations of cases where, with high probability, only symmetric variable orderings and, with high probability, only nonsymmetric variable orderings lead to minimum OBDD size are obtained. For this analysis estimates for the number of different blocks of random Boolean matrices are used. © 1998 John Wiley & Sons, Inc. Random Struct. Alg., 13, 49–70, 1998

Specific physical defects of high performance circuits manifest themselves as path delay faults (PDFs). A pair (v1, v2) of test patterns is required to detect a PDF. A PDF is robust testable if there is a test pair on which the fault manifestation does not depend on delays of other circuit paths. A PDF is non robust testable if manifestation of the fault on any test pair is possible only when all other paths of the circuit are fault free. For high quality delay testing it is desirable to detect delay of any path regardless of delays of other paths. In this paper, synthesis of a circuit by covering each nonterminal node of the reduced ordered binary decision diagram (ROBDD) or free binary decision diagram (Free BDD) system with the original subcircuit from gates is suggested. Delay testability of such circuits is investigated. It is specified that the PDF of each path of the circuit is detected without injecting additional inputs into the circuit. It is well known that the BDD is a directed acyclic graph based on the Shannon decomposition in each nonterminal node v: 0 1 i i x x v i v i v f x f x f = = = ∨ . Here fv is the function corresponding to the node v, and the decomposition variable xi marks the node v. The dashed edge drops in the node corresponding to the function 0 i x v f = , and the bold edge drops in the node corresponding to the function 1 i x v f = . The BDD is called ordered (OBDD) if variables are encountered in the same order in all paths connecting the BDD root with the terminal node. The BDD is called reduced (RBDD) if it does not contain either isomorphic subgraphs or nonterminal nodes such that 0 1 i i x x v v f f = = = . An example of reduced and ordered BDD (ROBDD) is shown in Fig. 1. When deriving the Free BDD, a suitable decomposition variable is chosen for each nonterminal node v independently of other nonterminal nodes. That may cut the number of Free BDD of nonterminal nodes in comparison with the ROBDD (for the same function). Let 1 { ,..., } m F f f = be a system of Boolean functions describing combinational circuit behavior. Derive the ROBDD using the same order of variables for each Boolean function from F. Join isomorphic subgraphs in different ROBDDs. Combine different ROBDDs of 1-terminal nodes into one 1-terminal node and their 0-terminal nodes into one 0-terminal node. As a result, we obtain the graph with m roots and two terminal nodes. This graph represents a system of m Boolean functions. It is called the shared ROBDD. Without loss of generality, we will further consider systems with one function as an example. In Fig. 1, the ROBDD for one Boolean function is shown. The ROBDD represents the disjoint sum of products (DSoP) of the function f as follows:

Translation among CNFs, characteristic models and ordered binary decision diagrams

The ordered binary decision diagram (OBDD) has proven useful in many applications as an efficient data structure for representing and manipulating Boolean functions. A serious drawback of OBDD's is the need for application-specific heuristic algorithms to order the variables before processing. Further, for many problem instances in logic synthesis, the heuristic ordering algorithms which have been proposed are insufficient to allow OBDD operations to complete within a limited amount of memory. The paper proposes a solution to these problems based on having the OBDD package itself determine and maintain the variable order. This is done by periodically applying a minimization algorithm to reorder the variables of the OBDD to reduce its size. A new OBDD minimization algorithm, called the sifting algorithm, is proposed and appears especially effective in reducing the size of the OBDD. Experiments with dynamic variable ordering on the problem of forming the OBDD's for the primary outputs of a combinational circuit show that many computations complete using dynamic variable ordering when the same computation fails otherwise.

Ordered Binary Decision Diagrams (BDDs) are a data structure for efficient representation and manipulation of Boolean functions. They are frequently used in logic synthesis and formal verification. The size of BDDs depends on a chosen variable ordering, i.e. the size may vary from linear to exponential, and the problem of improving the variable ordering is known to be NP-complete. In this paper we present a new exact branch & bound technique for determining an optimal variable order. In contrast to all previous approaches, that only considered one lower bound, our method makes use of a combination of three bounds and by this avoids unnecessary computations. The lower bounds are derived by generalization of a lower bound known from VLSI design. They allow to build the BDD either top down or bottom up. Experimental results are given to show the efficiency of our approach.

The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.

The relationship between two important means of representing Boolean functions, combinational circuits and ordered binary decision diagrams (OBDDs), is studied. Circuit width is related to OBDD size, and it is shown how register allocation can be used to determine a good variable order of OBDD construction. It is shown that if C has n inputs, m outputs, and width w(C), then there is a variable ordering for which the directed-acyclic-graph-based representation for C has at most n*m*2/sup w(C)/ nodes. Since the width of a circuit is closely related to the number of registers required to evaluate the circuit, the result shows that register allocation techniques can be used to compute variable orderings with predicted behavior. The use of these ideas in decomposing a function either for representation as a set of OBDDs or for implementation in a cascode technology is outlined. A characterization is given of a class of multioutput functions which includes addition whose members have particularly small OBDDs. >

The Nonapproximability of OBDD Minimization

The ordering of variables can have a significant effect on the size of the reduced binary decision diagram (BDD) that represents the set of solutions to a combinatorial optimization problem. It also influences the quality of the objective function bound provided by a limited-width relaxation of the BDD. We investigate these effects for the maximum independent set problem. By identifying variable orderings for the BDD, we show that the width of an exact BDD can be given a theoretical upper bound for certain classes of graphs. In addition, we draw an interesting connection between the Fibonacci numbers and the width of exact BDDs for general graphs. We propose variable ordering heuristics inspired by these results, as well as a k-layer look-ahead heuristic applicable to any problem domain. We find experimentally that orderings that result in smaller exact BDDs have a strong tendency to produce tighter bounds in relaxation BDDs.

Property testing is concerned with deciding whether an object (e.g. a graph or a function) has a certain property or is “far” (for a prespecified distance measure) from every object with that property. In this work we design and analyze an algorithm for testing functions for the property of being computable by a read-once width-2 Ordered Binary Decision Diagram (OBDD), also known as a branching program, where the order of the variables is not known to us. That is, we must accept a function f if there exists an order of the variables according to which a width-2 OBDD can compute f. The query complexity of our algorithm is $\tilde{O}({\rm log n}){\rm poly}(1/\epsilon)$. In previous work (in Proceedings of RANDOM, 2009) we designed an algorithm for testing computability by an OBDD with a fixed order, which is known to the algorithm. Thus, we extend our knowledge concerning testing of functions that are characterized by their computability using simple computation devices and in the process gain some insight concerning these devices.

The complexity of minimizing and learning OBDDs and FBDDs