Efficient Fault Tree Analysis of Complex Fault Tolerant Multiple-Phased Systems

Specific physical defects of high performance circuits manifest themselves as path delay faults (PDFs). A pair (v1, v2) of test patterns is required to detect a PDF. A PDF is robust testable if there is a test pair on which the fault manifestation does not depend on delays of other circuit paths. A PDF is non robust testable if manifestation of the fault on any test pair is possible only when all other paths of the circuit are fault free. For high quality delay testing it is desirable to detect delay of any path regardless of delays of other paths. In this paper, synthesis of a circuit by covering each nonterminal node of the reduced ordered binary decision diagram (ROBDD) or free binary decision diagram (Free BDD) system with the original subcircuit from gates is suggested. Delay testability of such circuits is investigated. It is specified that the PDF of each path of the circuit is detected without injecting additional inputs into the circuit. It is well known that the BDD is a directed acyclic graph based on the Shannon decomposition in each nonterminal node v: 0 1 i i x x v i v i v f x f x f = = = ∨ . Here fv is the function corresponding to the node v, and the decomposition variable xi marks the node v. The dashed edge drops in the node corresponding to the function 0 i x v f = , and the bold edge drops in the node corresponding to the function 1 i x v f = . The BDD is called ordered (OBDD) if variables are encountered in the same order in all paths connecting the BDD root with the terminal node. The BDD is called reduced (RBDD) if it does not contain either isomorphic subgraphs or nonterminal nodes such that 0 1 i i x x v v f f = = = . An example of reduced and ordered BDD (ROBDD) is shown in Fig. 1. When deriving the Free BDD, a suitable decomposition variable is chosen for each nonterminal node v independently of other nonterminal nodes. That may cut the number of Free BDD of nonterminal nodes in comparison with the ROBDD (for the same function). Let 1 { ,..., } m F f f = be a system of Boolean functions describing combinational circuit behavior. Derive the ROBDD using the same order of variables for each Boolean function from F. Join isomorphic subgraphs in different ROBDDs. Combine different ROBDDs of 1-terminal nodes into one 1-terminal node and their 0-terminal nodes into one 0-terminal node. As a result, we obtain the graph with m roots and two terminal nodes. This graph represents a system of m Boolean functions. It is called the shared ROBDD. Without loss of generality, we will further consider systems with one function as an example. In Fig. 1, the ROBDD for one Boolean function is shown. The ROBDD represents the disjoint sum of products (DSoP) of the function f as follows:

International Maritime Organization (IMO) implements the principles of risk management through a systematic process called Formal Safety Assessment (FSA). FSA is a structured and systematic methodology, aimed at enhancing maritime safety, including protection of life, health, the marine environment and property, by using risk analysis and cost benefit assessment. One of the most widely used hazard identification and risk analysis techniques in FSA is Fault Tree Analysis (FTA) method. However, only basic conventional methodology of the FTA technique is used in FSA. When dealing with large fault trees, the limitations of FTA in terms of accuracy and the efficiency become apparent. It is necessary for IMO to improve FTA method in FSA. In recent years, the Binary Decision Diagram (BDD) method has been developed that solves fault trees and overcomes the disadvantages of the conventional FTA approach. In this paper, the BDD method is introduced for the application in FSA, as it has never been used in FSA studies. A commonly used construction method and some basic event ordering methods of BDD are described. By applying BDD to FTA, two main issues concerned in FSA, minimal cut set and top event probability, can be obtained efficiently and accurately comparing to the analysis using a conventional FTA method.

Since their introduction in form of a canonical representation of logical functions, the Binary Decision Diagrams (BDDs) gained a wide acceptance in numerous industrial applications. This paper summarizes the properties of BDD representation of Minimal Cut Sets (MCS) of Fault Tree (FT) models most typically encountered in nuclear energetics. Cut sets from MCS are defined as paths from the top BDD node to terminal nodes in the BDD, on which a quantitative and qualitative FT analysis (FTA) is performed. The core of the FTA on the BDDs is performed with help of two fundamental algorithms, one for conditional probability evaluation and another for the selection of cut sets. The accuracy of conditional probability evaluation represents an essential feature for an unbiased quantitative analysis, such as the top event probability or the determination of event importance measures. The cut set selection algorithm is shown in a generic version introducing logical predicates for its selection criteria. As it is known, the efficiency of depicted algorithms depends only on the number of BDD nodes used for the FT representation. In order to appraise the compactness of the BDD representation of FT models, their characteristics have herein been evaluated on several real-life models from the Nuclear Power Plant Krško. The extraordinariness of the compactness of the BDD representation reflects in its ability to implement advanced dynamic analysis (i.e. what-if) of FT models. The efficiency of such an approach is recognized by commercial vendors upgrading their FT Tools to new versions by implementing BDD based algorithms.

While most of the research efforts on network reliability analysis have focused on networks with imperfect links but perfectly reliable nodes, binary decision diagram–based methods have recently been developed to determine reliability of networks with imperfect links and imperfect nodes. The smaller the binary decision diagram size is, the better the performance of the binary decision diagram–based algorithm will be. The binary decision diagram size heavily depends on the chosen variable ordering. As finding the optimal variable ordering is a nondeterministic polynomial time-complete problem, a heuristic is typically used. Various heuristics based on depth-first search, breadth-first search, and network-driven search have been developed for network reliability analysis. However, they often assume the networks have perfectly reliable nodes. This article advances the state-of-the-art by proposing a new ordering heuristic for the binary decision diagram–based reliability analysis of networks with imperfect links/edges and nodes. Empirical studies show that the proposed new ordering heuristic can generate significantly smaller binary decision diagram size for a wide variety of network structures than the traditional depth-first search–based, breadth-first search–based, network-driven search–based heuristics for most cases, enabling efficient binary decision diagram–based reliability analysis of large-scale networks considering both link and node failures. Robustness of the proposed heuristic is also investigated through empirical studies.

The size of ordered binary decision diagrams (OBDDs) strongly depends on the chosen variable ordering. It is an obvious heuristic to use symmetric variable orderings, i.e., variable orderings where symmetric variables are arranged adjacently. In order to evaluate this heuristic, methods for estimating the OBDD size for random partially symmetric functions are presented. Characterizations of cases where, with high probability, only symmetric variable orderings and, with high probability, only nonsymmetric variable orderings lead to minimum OBDD size are obtained. For this analysis estimates for the number of different blocks of random Boolean matrices are used. © 1998 John Wiley & Sons, Inc. Random Struct. Alg., 13, 49–70, 1998

An ordered binary decision diagram (OBDD) is a directed acyclic graph that represents a Boolean function. Since OBDDs have many nice properties as data structures, they have been extensively studied for decades in both theoretical and practical fields, such as VLSI (Very Large Scale Integration) design, formal verification, machine learning, and combinatorial problems. Arguably, the most crucial problem in using OBDDs is that they may vary exponentially in size depending on their variable ordering (i.e., the order in which the variables are to be read) when they represent the same function. Indeed, it is NP hard to find an optimal variable ordering that minimizes an OBDD for a given function. Friedman and Supowit provided a clever deterministic algorithm with time/space complexity O^∗(3ⁿ), where n is the number of variables of the function, which is much better than the trivial brute-force bound O^∗(n!2ⁿ). This paper shows that a further speedup is possible with quantum computers by presenting a quantum algorithm that produces a minimum OBDD together with the corresponding variable ordering in O^∗(2.77286ⁿ) time and space with an exponentially small error probability. Moreover, this algorithm can be adapted to constructing other minimum decision diagrams such as zero-suppressed BDDs.

In real‐world systems, component failures can be categorized into local failures (LF) and propagated failures (PFs). The PFs from components not only cause their own malfunction but also affect other components within the systems. However, in systems with functional dependence behavior, if a component (referred to as trigger component) fails before the PFs of components (referred to as dependent components) happen, it can isolate the PFs, thus preventing PFs from affecting other components; otherwise, the failure propagation effect occurs, causing extensive damage to the entire system. The competition between failure propagation and isolation shows a significant challenge in analyzing the reliability of the systems. This paper proposes an efficient combinatorial method based on binary decision diagram (BDD), referred to as BDD reuse method, for the reliability analysis of systems subject to competing failures. Compared to the traditional methods of generating multiple reduced fault trees and BDDs, this method generates only one fault tree and one BDD. An intelligent ward call system example is provided to demonstrate the application of the proposed method. The accuracy of the method is proved by Monte Carlo simulation. The performance is analyzed and compared with the traditional methods. In addition, the variable ordering strategy is studied, and a BDD reduction and evaluation method is proposed to further improve the efficiency of the method.

Translation among CNFs, characteristic models and ordered binary decision diagrams

The ordered binary decision diagram (OBDD) has proven useful in many applications as an efficient data structure for representing and manipulating Boolean functions. A serious drawback of OBDD's is the need for application-specific heuristic algorithms to order the variables before processing. Further, for many problem instances in logic synthesis, the heuristic ordering algorithms which have been proposed are insufficient to allow OBDD operations to complete within a limited amount of memory. The paper proposes a solution to these problems based on having the OBDD package itself determine and maintain the variable order. This is done by periodically applying a minimization algorithm to reorder the variables of the OBDD to reduce its size. A new OBDD minimization algorithm, called the sifting algorithm, is proposed and appears especially effective in reducing the size of the OBDD. Experiments with dynamic variable ordering on the problem of forming the OBDD's for the primary outputs of a combinational circuit show that many computations complete using dynamic variable ordering when the same computation fails otherwise.

Introducing Temporal Behaviour into Binary Decision Diagrams

An ordering heuristic to develop the binary decision diagram based on structural importance

Optimal ordered binary decision diagrams for read-once formulas

The binary decision diagram is a graph representation of Boolean functions, it also can efficiently represent the logic functionality of digital circuits. The number of nodes in binary decision diagram depends on the variable ordering. A new method is presented in this paper for the variable ordering and the minimization of binary decision diagram, the method is based on adaptive hierarchy genetic algorithm, which uses two populations with hierarchy to evolve in parallel, and the operation parameters in the evolution procedure are adjusted dynamically as the changes of environment. The individual representation scheme corresponding to binary decision diagram, and the implementation steps of adaptive hierarchy genetic algorithm, are given in detail. Besides, the application of the method for the test generation of digital circuits is given. A lot of experimental results show that the binary decision diagrams with smaller number of nodes can be obtained by the method proposed in this paper, and the test vectors of faults in digital circuits can also be produced.

Property testing is concerned with deciding whether an object (e.g. a graph or a function) has a certain property or is “far” (for a prespecified distance measure) from every object with that property. In this work we design and analyze an algorithm for testing functions for the property of being computable by a read-once width-2 Ordered Binary Decision Diagram (OBDD), also known as a branching program, where the order of the variables is not known to us. That is, we must accept a function f if there exists an order of the variables according to which a width-2 OBDD can compute f. The query complexity of our algorithm is $\tilde{O}({\rm log n}){\rm poly}(1/\epsilon)$. In previous work (in Proceedings of RANDOM, 2009) we designed an algorithm for testing computability by an OBDD with a fixed order, which is known to the algorithm. Thus, we extend our knowledge concerning testing of functions that are characterized by their computability using simple computation devices and in the process gain some insight concerning these devices.

The complexity of minimizing and learning OBDDs and FBDDs