Quantum dot gate non-volatile memory as single level cell (SLC), multi-level cell (MLC) and triple level cell (TLC)

Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.

In this paper, different architectures for the ternary logic inverter using quantum dot gate non-volatile memory (QDNVM), are introduced. Ternary logic inverters with resistive load and NMOS architecture are designed and explained. The CMOS architecture of the ternary logic inverter is also introduced. The uniform noise margin in the QDNVM circuit is very promising. The implementation of ternary logic circuits using QDNVM will help to implement multivalued logic (MVL) for different applications in the future.

Transformers, while revolutionary, face challenges due to their demanding computational cost and large data movement.To address this, we propose HyFlexPIM, a novel mixed-signal processingin-memory (PIM) accelerator for inference that flexibly utilizes both single-level cell (SLC) and multi-level cell (MLC) RRAM technologies to trade-off accuracy and efficiency.HyFlexPIM achieves efficient dual-mode operation by utilizing digital PIM for highprecision and write-intensive operations while analog PIM for high parallel and low-precision computations.The analog PIM further distributes tasks between SLC and MLC PIM operations, where a single analog PIM module can be reconfigured to switch between two operations (SLC/MLC) with minimal overhead (<1% for area & energy).Critical weights are allocated to SLC RRAM for high accuracy, while less critical weights are assigned to MLC RRAM to maximize capacity, power, and latency efficiency.However, despite employing such a hybrid mechanism, brute-force mapping on hardware fails to deliver significant benefits due to the limited proportion of weights accelerated by the MLC and the noticeable degradation in accuracy.To maximize the potential of our hybrid hardware architecture, we propose an algorithm co-optimization technique, called gradient redistribution, which uses Singular Value Decomposition (SVD) to decompose and truncate matrices based on their importance, then fine-tune them to concentrate significance into a small subset of weights.By doing so, only 5-10% of the weights have dominantly large gradients, making it favorable for HyFlexPIM by minimizing the use of expensive SLC RRAM while maximizing the efficient MLC RRAM.Our evaluation shows that HyFlexPIM significantly enhances computational throughput and energy efficiency, achieving maximum 1.86 and 1.45 higher than state-of-the-art methods.

Conventional DRAM and flash memory are reaching their scaling limits thus motivating research in various emerging memory technologies as a potential replacement. Among these, phase change memory (PCM) has received considerable attention owing to its high scalability and multi-level cell (MLC) operation for high storage density. However, due to the resistance drift over time, the soft error rate in MLC PCM is high. Additionally, the iterative programming in MLC negatively impacts performance and cell endurance. The conventional methods to overcome the drift problem incur large overheads, impact memory lifetime and are inadequate in terms of acceptable soft error rate (SER). In this paper, we propose a new PCM memory architecture with heterogeneous PCM arrays to increase reliability, performance and lifetime. The basic storage unit in the proposed architecture consists of two single-level cells (SLCs) and one four-level cell (4LC). Using the reduced number of 4LCs compared to conventional homogeneous 4LC PCM arrays, the drift-induced error rate is considerably reduced. By alternating each cell operation between SLC and 4LC over time, the overall lifetime can also be significantly enhanced. The proposed architecture achieves up to 105 times lower soft error rate with considerably less ECC overhead. With simple ECC scheme, about 22% performance improvement is achieved and additionally, the overall lifetime is also enhanced by about 57%.

A hybrid flash translation layer design for SLC–MLC flash memory based multibank solid state disk

Computing-in-memory (CiM) architectures have experienced faster growth with the emergence of nanoscale magnetic tunnel junction (MTJ) spintronic devices due to their nonvolatile and CMOS compatible architectures. Recently, spin-transfer torque (STT) and spin Hall effect (SHE)-based several CiM designs have been published. The majority of these designs employ a single-level cell (SLC) memory array and require high write energy to perform logic computations. To mitigate these problems, we propose novel SLC and multilevel cell (MLC) differential spin Hall (DSH) magnetic random access memory (MRAM)-based CiM designs that employed MTJs with field-free switching technique using the in-plane magnetic (IPM) layer. Initially, SLC DSH-MRAM-based magnetic full adder (MFA) is proposed. Furthermore, DSH-MRAM series MLC (sMLC)-based CiM implementations of AND/OR/XOR gates and 1 bit MFA are presented in this work. This DSH-sMLC-based CiM structure exploits a reconfigurable precharge sense amplifier (RPCSA) and innovative MTJ reference mechanism to perform each of the logic operations within a single evaluation cycle and provides complementary logic outputs useful for further computations. The comparative performance analysis of the proposed CiM MFA with SHE-based and voltage-controlled SHE-sMLC-based CiM designs reveals 52% and 33% improvement in write energy, respectively. The proposed design saves 34% area compared to the SHE-based counterpart.

Green cloud is an emerging new technology in the computing world in which memory is a critical component. Phase-change memory (PCM) is one of the most promising alternative techniques to the dynamic random access memory (DRAM) that faces the scalability wall. Recent research has been focusing on the multi-level cell (MLC) of PCM. By precisely arranging multiple levels of resistance inside a PCM cell, more than one bit of data can be stored in one single PCM cell. However, the MLC PCM suffers from the degradation of performance compared to the single-level cell (SLC) PCM, due to the longer memory access time. In this paper, we present a genetic-based optimization algorithm for chip multiprocessor (CMP) equipped with PCM memory in green clouds. The proposed genetic-based algorithm not only schedules and assigns tasks to cores in the CMP system, but also provides a PCM MLC configuration that balances the PCM memory performance as well as the efficiency. The experimental results show that our genetic-based algorithm can significantly reduce the maximum memory usage by 76.8 percent comparing with the uniform SLC configuration, and improve the efficiency of memory usage by 127 percent comparing with the uniform 4 bits/cell MLC configuration. Moreover, the performance of the system is also improved by 24.5 percent comparing with the uniform 4 bits/cell MLC configuration in terms of total execution time.

Quantized Key-Value (KV) cache is a remarkable technology to reduce the memory footprint during LLM inference. While multi-level cell (MLC) ReRAM offers higher density than single-level cell (SLC) ReRAM, its current fluctuation, often induced by random telegraph noise, leads to false detection of cell state and degraded reliability. This work explores a strategy to store quantized KV cache in ReRAM to reduce memory area, while maintaining LLM performance. This study analyzes the error robustness of the three constituent components of the quantized KV cache. The proposal splits the value of each component into the upper bits and the lower bits, then stores the upper bits in SLC ReRAM and the lower bits in MLC ReRAM. This work achieves 49.1% fewer memory cells than the conventional method while maintaining the perplexity at a low level, regardless of LLMs and quantization methods.

The non-volatile memory (NVM) is becoming the main device of next-generation memory, due to the high density, near-zero standby power, non-volatile and byte-addressable features. The multi-level cell (MLC) technique has been used in non-volatile memory to significantly increase device density and capacity, which however leads to much weaker endurance than the single-level cell (SLC) counterpart. Although wear-leveling techniques can mitigate this weakness in MLC, the improvements upon MLC-based NVM become very limited due to not achieving uniform write distribution before some cells are really worn out. To address this problem, our paper proposes a self-adaptive wear-leveling (SAWL) scheme for MLC-based NVM. The idea behind SAWL is to dynamically tune the wear-leveling granularities and balance the writes across the cells of entire memory, thus achieving suitable tradeoff between the lifetime and cache hit rate. Moreover, to reduce the size of the address-mapping table, SAWL maintains a few recently-accessed mappings in a small on-chip cache. Experimental results demonstrate that SAWL significantly improves the NVM lifetime and the performance, compared with state-of-the-art schemes.

This paper proposes a mix-and-match design method for triple level cell (TLC)/multi level cell (MLC) NAND flash hybrid and exchangeable storage arrays. A TLC-NAND flash provides an low cost and high capacity memory solution. However the reliability and access latency of TLC NAND flash are degraded from MLC NAND flash. Additionally, the block unit write is preferable for TLC NAND flash since the write order is complicated due to narrow data margin and write disturbance. The proposed solution combines TLC and MLC NAND flash memories for a storage array. To reduce access to TLC NAND flash, the stored data is screened and only the static frozen data are stored into TLC NAND flash with a Round-Robin frozen data collection algorithm (RR-FDCA). Furthermore, the proposed chip exchanging method extends the solid-state drive (SSD) lifetime without system suspending. As a result, in spite of moderate characteristics of TLC NAND flash, the proposed storage array can achieve 29% write energy saving and 56% write performance enhancement with 17% cost reduction, compared with the conventional MLC-only SSD.

This paper proposes a novel multi-level cell spin-orbit torque magnetic random-access memory (MLC SOT-MRAM) cell structure and validates its functionality and performance through simulation. The proposed memory cell comprises two uniform magnetic tunnel junctions (MTJs) that can be programmed separately by the energy efficient SOT technology through two different heavy metal electrodes. This permit employing both single and dual port architectures. The uniform cross-sectional area of the in-series MTJs stack simplifies the fabrication process. In addition, the cell structure requires only four terminals to successfully read and write the two bits. This allows accessing the two bits with only three access transistors, which achieves 25% smaller 1-bit effective area compared to the conventional single level cell (SLC) SOT-MRAM that requires four transistors. Simulation results based on an approximated dynamic model shows it offers nearly similar write energy consumption compared to the conventional SOT-MRAM.

Multi-level memory cells are used in non-volatile memories in order to increase the storage density. Using multi-level cells, however, imposes higher read and write latencies limiting high speed applications. In this work we study the tradeoff between storage density and write/read performance using codes. The contributions are codes that give high-performance write and read processes with minimal reduction in storage density. We describe the codes, give an analytical treatment of their information rate and speed, and compare them with more basic access schemes and upper bounds.

The ever increasing demand to store huge amounts of data at affordable prices has led to the widespread usage of multi level cell (MLC) memory devices. These memories have the capability to store multiple numbers of bits per cell, thus increasing the capacity with minimal effect on hardware. This increase, however, comes at the price of reliability; more bits per cell results in more chances of error and thus less reliability. Error control coding is widely employed to improve the reliability of data that has been read. This paper proposes a new scheme for error correction in multilevel cell memories. The process involves splitting the contents of the memory cells into i symbols and assigning them to i different codewords. Encoding and decoding are performed using the same code but over i iterations. The scheme exhibits an apparent error correction advantage over polyvalent-based schemes.

Spin-transfer torque magnetic random access memory (STT-RAM) technology has emerged as a potential replacement of SRAM in cache design, especially for building large-scale and energy-efficient last level caches. Compared with single-level cell (SLC), multi-level cell (MLC) STT-RAM is expected to double cache capacity and increase system performance. However, the two-step read/write access schemes incur considerable energy consumption and performance degradation. In this paper, we propose two techniques using data compression to optimize MLC STT-RAM cache design. The first technique tries to compress a cache line and fit it into only the soft-bit region of the cells, so that reading or writing this cache line takes only one step which is fast and energy-efficient. We introduce a second technique to increase the cache capacity by enabling the left hard-bit region to store another compressed cache line, which can improve the system performance for memory intensive workloads. The experimental results show that, compared with a conventional MLC STT-RAM last level cache design, our overhead minimized technique reduces the dynamic energy consumption by 38.2% on average with the same system performance, and our capacity augmented technique boosts the system performance by 6.1% with 19.2% dynamic energy saving on average, across the evaluated multi-programmed benchmarks.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.