Area Efficient High Through-put Dual Heavy Metal Multi-Level Cell SOT-MRAM

This paper presents a spin-orbit torque magnetic random access memory (SOT-MRAM) using perpendicular-anisotropy magnetic tunnel junction (p-MTJ). In spite of conventional p-MTJ based SOT-MRAMs which need an external magnetic field to achieve a deterministic switching, the proposed cell uses a spin-torque transfer (STT) current where we show that the cell needs only two access transistors. This can solve the thermal instability, complexity and process variation sensitivity issues of the conventional SOT-MRAMs. In addition, it maintains the advantage of conventional p-MTJ based SOT-MRAMs such as ultra-fast switching and enhanced reliability of the MTJ. Our simulation results show that the proposed SOT-MRAM can achieve 3.3X and 2.8X faster and energy efficient write operation in comparison with the conventional SOT-MRAMs.

This paper presents a multilevel spin-orbit torque magnetic random access memory (SOT-MRAM). The conventional SOT-MRAMs enables a reliable and energy efficient write operation. However, these cells require two access transistors per cell, hence the efficiency of the SOT-MRAMs can be questioned in high-density memory application. To deal with this obstacle, we propose a multilevel cell which stores two bits per memory cell. In addition, we propose a novel sensing scheme to read out the stored data in the multilevel SOT-MRAM cell. Our simulation results show that the proposed cell can achieve 3X more energy efficient write operation in comparison with the conventional STT-MRAMs. In addition, the proposed cell store two bits without any area penalty in comparison to the conventional one bit SOT-MRAM cells.

As an emerging non-volatile memory technology, the spin orbit torque magnetic random access memory (SOT-MRAM) has attracted intensive research interest due to its advanced performance. However, the binary storage feature of the SOT-MRAM has become one of the obstacles. In this paper, we present a study of two-bit multi-level SOT-MRAM where two canted in-plane-anisotropy magnetic tunnel junctions (MTJs) store a pair of data. Compared with the previous schemes of multi-level SOT-MRAMs, our proposal enables fully one-step writing without the need of the preset operation. Micromagnetic simulation is performed to validate the functionality of the proposed multi-level cell (MLC) SOT-MRAM, meanwhile, the details of magnetization switching are clearly shown. Simulation results also demonstrate that the device could accomplish the magnetization switching at the sub-nanosecond speed and continuously decreasing power consumption with the size scaling down. In addition, the dipolar field between two cells has little influence on the switching process.

This paper presents the application of quantum dot gate non-volatile memory (QDNVM) for single-level, multi-level and triple level memory cell. The charge accumulation in the gate region varies the threshold voltage of QDNVM which can be controlled by the application of external gate pulse. More pulse helps to tunnel more charge carriers form the inversion channel to the Quantum dot (QD) layer in the gate region of the QDNVM. The varying stored charge in the QD layer of the QDNVM, varies the threshold voltage of the device. By controlling the applied gate voltage pulse, the QDNVM can be used for single level cell (SLC), multi-level cell (MLC) and triple level Cell (TLC). A simplified circuit model using VHDL is developed for QDNVM. This work will highlight future memory integration using QDNVM.

Computing-in-memory (CiM) architectures have experienced faster growth with the emergence of nanoscale magnetic tunnel junction (MTJ) spintronic devices due to their nonvolatile and CMOS compatible architectures. Recently, spin-transfer torque (STT) and spin Hall effect (SHE)-based several CiM designs have been published. The majority of these designs employ a single-level cell (SLC) memory array and require high write energy to perform logic computations. To mitigate these problems, we propose novel SLC and multilevel cell (MLC) differential spin Hall (DSH) magnetic random access memory (MRAM)-based CiM designs that employed MTJs with field-free switching technique using the in-plane magnetic (IPM) layer. Initially, SLC DSH-MRAM-based magnetic full adder (MFA) is proposed. Furthermore, DSH-MRAM series MLC (sMLC)-based CiM implementations of AND/OR/XOR gates and 1 bit MFA are presented in this work. This DSH-sMLC-based CiM structure exploits a reconfigurable precharge sense amplifier (RPCSA) and innovative MTJ reference mechanism to perform each of the logic operations within a single evaluation cycle and provides complementary logic outputs useful for further computations. The comparative performance analysis of the proposed CiM MFA with SHE-based and voltage-controlled SHE-sMLC-based CiM designs reveals 52% and 33% improvement in write energy, respectively. The proposed design saves 34% area compared to the SHE-based counterpart.

The non-volatile spin–orbit torque magnetic random access memory (SOT-MRAM) is a very attractive memory technology for near future computers because it has various advantages such as non-volatility, high density and scalability. In the present work we propose a model of a graphene recording device for the SOT-MRAM unit cell, consisting of a quasi-freestanding graphene intercalated with Au and an ultra-thin Pt layer sandwiched between graphene and a magnetic tunnel junction. As a result of using the claimed graphene recording memory element, a faster operation and lower energy consumption will be achieved under the recording information by reducing the electric current required to record. The efficiency of the graphene recording element was confirmed by the experimental results and the theoretical estimations.

We investigated and compared the structural and magnetic properties of MgO/FeCoB based out-of-plane magnetized tunnel junctions at the thin film level and the magneto-transport properties of the corresponding patterned spin transfer torque magnetic random access memory(STT-MRAM) cells comprising either Ta1 nm or W2/Ta1 nm cap layers for different annealing temperatures up to 455 °C. The W material in the cap was found to improve the structural stiffness of the perpendicular magnetic tunnel junctions (pMTJs) and most importantly prohibits Fe diffusion from the FeCoB storage layer to the cap layer, remarkably improving the thermal robustness and magneto-transport properties of the stacks and of the corresponding patterned memory cells. As a result, the interfacial anisotropy constant of the MgO/FeCoB interfaces is improved by 17%–29% compared to the Ta cap. The STT-MRAM cells fabricated from the pMTJ stacks with the W/Ta cap reveal a significant improvement of the tunneling magnetoresistance and thermal stability factor, which are 120% and 52 as compared to 70% and 35 for the stack with the Ta cap, respectively. This improvement is ascribed to the enhancement of MgO crystallinity upon higher temperature annealing (425 °C) and prohibition of Fe out-diffusion.

Back-hopping type soft errors and etching-induced shunting failure are among the primary failure mechanisms preventing spin-orbit torque magnetic random access memory (SOT-MRAM) technology from commercialization. In this work, a novel writing scheme is proposed, which effectively suppresses back-hopping type soft failures, achieving a writing error rate below 1 ppm and a significantly widened write margin for enhanced reliability. Meanwhile, by inserting a buffer layer between the free layer and the SOT layer, we demonstrated significantly reduced shunting failure, yield improvement, and a raw bit error rate down to 52 ppm on 300 mm wafers. Additionally, a high-yield magnetic tunnel junction with a tunnel magnetoresistance (TMR) of 134% is demonstrated through material and stack optimization. These progresses pave the way for the development of high-density SOT-MRAM chips with Mbit~Gbit capacities.

Spin-orbit torque (SOT)-based in-memory logic designs offer a promising approach to alleviating the memory wall problem. However, in existing schemes, the basic cells mainly rely on auxiliary physical mechanisms or transistors, which considerably limit their applicability. In this work, we demonstrate a novel SOT-based device fabricated on an 8-inch wafer platform, featuring dual canted magnetic tunnel junctions (MTJs) monolithically integrated via a well-designed SOT channel. This device breakthrough simultaneously achieves fast switching (current density is 19.8 MA/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>@5 ns), multi-bit storage, and in-memory logic operations via SOT alone, while maintaining compatibility with CMOS technology (σ% under 7.25% in arrays). By exploiting synergistic voltage control, we achieve <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in situ</i> XOR operation and edge detection with error tolerance and competitive F-measure. Our proposed scheme provides a potential pathway toward next-generation large-scale, ultra-fast, and energy-efficient in-memory logic.

We have developed a write-line-inserted magnetic tunneling junction (MTJ) (WLIM) for use in low-write-current magnetoresistance random access memory (MRAM). The write current of the WLIM was reduced to 0.98mA and its thermal stability factor was 85 for a 0.32×0.48μm2 MTJ. We evaluated the switching property of the WLIM in an external magnetic field (Hsw̱ext) and an internal magnetic field (Hsw̱int). We found that Hsw̱ext was larger than Hsw̱int when the aspect ratio of the MTJs was less than 1.5. Furthermore, we obtained a high write-current magnetic-field efficiency of 13.0Oe∕mA when the aspect ratio of the MTJs was low. These properties mean that the WLIM structure has advantages for use in low-write-current MRAM.

This paper describes newly developed magnetic random access memory (MRAM) cell technology suitable for high-speed memory macros embedded in next-generation system LSIs: a two-transistor one-magnetic tunneling junction (2T1MTJ) cell structure, a write-line-inserted MTJ, and a 5T2MTJ cell structure. The 2T1MTJ cell structure makes it possible to significantly improve the write margin and accelerate the operating speed to 200 MHz. Its high compatibility with SRAM specifications and its wide write margin were confirmed by measuring 2T1MTJ MRAM test chips. Although the cell structure requires a small-writing-current MTJ, the current can be reduced to 1mA using the newly developed write-line-inserted MTJ. Further development to reduce the current down to 0.5 mA is required to obtain a cell area of 1.9 mum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , which is smaller than the SRAM cell area, in the 0.13-mum CMOS process. The 5T2MTJ cell structure also enables random-access operation over 500 MHz because the sensing signal is amplified in each cell. Random access time of less than 2 ns can be achieved with SPICE simulation when the magnetic resistance is 5 kOmega and the magnetoresistive (MR) ratio is more than 70%

For each case of current and voltage detection in series connections, and current and voltage in parallel connections in the multi‐layered structure of a magnetoresistive random access memory (MRAM) cell having two serially connected magnetic tunnel junction (MTJ) layers, first, we demonstrate the existence of an optimum value for the weighting coefficientkof the resistance, the voltage dependence, and the dependence on the magnetic resistance (MR) of the MTJ. Therefore, to optimize the signal margin in multiple layers, the ability to detect series connections with high sensitivity up to an MR ratio of 1 is demonstrated quantitatively. © 2007 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 90(3): 42–48, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.20265

In recent years, spin-transfer torque magnetoresistive random access memory (STT-MRAM) has gained a lot of interest as a promising memory candidate for future embedded applications. STT-MRAM possesses desirable memory attributes such as excellent readability, writability, stability, non-volatility, and unlimited endurance. Moreover, ITRS reports that STT-MRAM can endure 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup> cycle operations before breakdown thus meeting 10 yrs life-time. As shown in Fig. 1, STT-MRAM bitcell consists of one access transistor and one magnetic tunnel junction (MTJ) (1T-1R). One of the primary reliability concerns in STT-MRAM is the dielectric breakdown of the tunnel junction MgO in the MTJ known as time-dependent dielectric breakdown (TDDB). The thickness of MgO is on the order of 1nm and the voltage across the MTJ during write operation is approximately 0.7V resulting in electric field of ~10MV/cm across it which can induce TDDB. Thus, such high stress conditions can lead to lower breakdown time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BD</sub> ) which can go even lower with further MgO thickness scaling. In addition to the hard breakdown (HBD) in MTJ which results in very low MTJ impedance and inability to function as memory, experimental results show that soft breakdowns (SBD) also exists. SBDs cause minor degradation in the MTJ resistance and they have shorter average time to appear compared to HBDs. In this paper, we explore in detail the physical mechanism behind both HBD and SBD, and using percolation model we estimate the time dependent degradation in the MTJ performance parameters such as tunneling magneto-resistance (TMR), write current (J <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ), write-time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">WR</sub> ) and lifetime (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LIFE</sub> ).

As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various and segmented system to fill the gap between the current memory systems in terms of the cost and performance. The nonvolatile memory will upgrade the current memory subsystems and enable the stable system architectures that retain their state even when power is off. The emerging memories will not directly replace the existing memory (DRAM and Flash memory) but will make a new memory class. The attributes of STT-MRAM can lead to adopt in-memory computing architectures for the embedded memory solution SoC. In these circumstances, the accurate and scalable model of magnetic tunnel junction (MTJ) is required to accelerate the commercialization of STT-MRAM. In this thesis, after the MTJ basics is introduced as a storage element and the magnetic dynamics to utilize the electron spins as wells as the electron charges, the parallel and anti-parallel magnetization configuration is explained in terms of the band structure to understand the basic operation of the MTJ in memory cell. To demonstrate the viability of MTJ as a memory cell, the switching mechanism, reading/writing scheme, and some important parameters in STT-MRAMs such as TMR (Tunneling Magnetoresistance), Switching current (Ic), and Thermal Stability (Δ) are investigated. As a test vehicle of the technology, a set of RAM is designed in this research to show its efficiency and advantages of MTJ memory cell. As a first step of the design, the scalable model of a MTJ that accurately depicts the spin-transfer torque dynamic switching behavior of a MTJ is verified along with its bias voltage and Temperature dependency. The model integrates the physical models of static and dynamic behaviors; many experimental parameters are provided to see the process variations, especially temperature and bias voltage perspective. Based on the verified model, a set of RAM circuit is designed, and the designed STT-MRAM circuit's behavior and performances are analyzed to find the optimum tunnel magnetoresistance (TMR) ratio and switching performance. Of the compact model of the CoFeB/MgO PMA-MTJ (perpendicular magnetic anisotropy MTJ). The whole circuit was designed in a standard 45nm CMOS technology using MTJ. The measurement shows that the switching delay of MTJ increases by 5.5ns with growing tunnel barrier oxide (MgO) thickness from 0.85nm to 1.15nm. A bit longer delay for writing is observed as expected. The simulation shows a trade-off between memory access time and MTJ area as the switching delay of MTJ decreases by 6.5ns when the MTJ area increases from 1010nm to 4040nm. For reading operation of the memory, the conventional sense amplifier circuit is employed to detect the stored bit-cell. In the reading peripheral circuits including sense amplifier, the fixed reference voltage (0.9V) is used to simplify the analysis. The reading operation and peripheral block of memory circuits is verified successfully with read access time of 1.47ns.--Author's abstract

To make spin–orbit torque magnetic random access memory (SOT-MRAM) practical, current-induced magnetization switching without an external bias field is essential. Given that the CoFeB/MgO structure has already been used in typical spin-transfer torque-MRAM for its high tunneling magnetoresistance, leveraging a similar material system to achieve field-free SOT switching is of great importance. In this work, we systematically investigate the field-free switching mechanism in CoFeB/W/CoFeB T-type structures, where the two CoFeB layers are in-plane and perpendicularly magnetized, respectively. Initial SOT characterization shows a sizable zero-field SOT efficacy (χHx=0) for such T-type devices. Furthermore, field-free angle-dependent SOT measurement confirms the parallel relationship between the built-in bias field and the magnetization of the in-plane magnetized CoFeB. Based on thorough verification and exclusion of other potential mechanisms, the Néel orange-peel effect emerges as the dominant origin for such a built-in bias field, where a positive correlation between the deposited film surface roughness and χHx=0 is found. Based on this discovery, the field-free switching efficacy in T-type structures is further optimized via film roughness tuning and examined with pillar-shaped devices. Our results provide insights into the tentative approach to improve field-free switching using T-type devices and the feasibility of downscaling.