Real-Time Analysis of Low-Cost Software-Defined Radio Transceiver Using ZigBee Protocol

Cyber is concerned with networks of systems in all their possible forms. Electronic warfare (EW) is focused on the many different uses of the electromagnetic spectrum (EMS). Given that many networks make use of the EMS (wireless networks), there is clearly large scope for collaboration between the cyber-warfare and EW communities. Unfortunately, such collaboration is complicated by the significant differences between these two realms. Software-defined radio (SDR) systems are based on interfaces between the EMS and computers and thus offer tremendous potential for encouraging cyber-EW collaboration. The concept of SDR is reviewed along with some hardware and software SDR systems. These are then used to propose a number of projects where SDR systems allow collaboration between the cyber and EW realms to achieve effects which neither realm could achieve alone.

The ultimate objective of Software Defined Radio (SDR) is to replace the entire analog signal processing in the wireless transceivers with digital signal processing. This will provide the flexibility, through reconfiguration or reprogramming, to enable the transceivers to work with different air-interfaces standards using a single generic hardware platform. Most of the research in SDR to date has been focused on base stations, which do not have as tight constraints in size and power consumption as handsets. However, in order to realize the promise of integrated services and global roaming capabilities, the design and development of a multi-standard SDR handset with dynamic reconfigurability is crucial. The size and power constraints imposed by handsets with limited resources pose a major design challenge. This special issue brings together 11 papers that address various aspects of this challenge from the perspectives of wireless systems, computing architectures, embedded systems and signal processing. The most important part of an SDR transceiver is the wideband analog-to-digital converter (ADC) that converts the radio frequency signal received by the antenna into digital form for further processing. The first paper, “A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications” by Jose et. al. proposed a cascaded reconfigurable sigma-delta modulator that is able to work with three different communication standards. This design, implemented in 0.18 μm CMOS technology, exhibits excellent signal-to-noise plus distortion ratios and has reduced power consumption compared to conventional designs. After ADC, the digitized received signal will need to be separated into signals within the various bands specified by the communication standard. This is performed by the channelizer which has the highest computational requirements of the whole SDR system. The second paper, by Panicker et al., reviews the state-of-the-art filter bank channelizer techniques with low power and dynamic reconfigurability properties. The design of reconfigurable devices can be optimized using the methodology of parametrization which bring together the common aspects of a myriad number of wireless standards into a single processing procedure. In this way, the implementation of the multi-standard SDR will be greatly simplified. “Promising technique of parametrisation for reconfigurable radio, the Common Operators Technique: fundamentals and examples” by Alaus et al. presents the common operator technique for parametrization which is less standards dependent than the more conventional Common Function technique. The direct digitization of the radio frequency (RF) signal requires very high speed ADCs which is not readily available using current technology. Therefore, current SDR implementations typically down-converts the RF A. P. Vinod (*) School of Computer Engineering, Nanyang Technological University, Nanyang, Singapore e-mail: asvinod@ntu.edu.sg

The availability of commercial Radio Frequency System on Chip (RFSoC) devices brings new possibilities for implementing Software Defined Radio (SDR) systems. Such systems are of increasing interest given the pace of innovation in wireless technology, and the pressure on RF spectrum resources, leading to a growing need to access the spectrum in more dynamic and innovative ways. In this paper, we present an SDR demonstration system based on the Xilinx RFSoC platform, which leverages the Python-based ‘PYNQ’ (Python Productivity for Zynq) software framework. In doing so, we highlight features that can be extremely useful for prototyping radio system design. Notably, our developed system features Python-based control of hardware processing blocks and Radio Frequency (RF) data converters, as well as direct visualisation of communications signals captured within the chip. The system architecture is reviewed, hardware and software components are discussed, functionality is demonstrated, and aspects of the system’s performance are evaluated. Finally, it is noted that this combined RFSoC + PYNQ approach is readily extensible for other SDR systems; we highlight our online shared resources, and invite other engineers to investigate and build upon our work.

Fast Fourier Transform (FFT) is computationally an efficient algorithm that transforms a function in time domain to function in frequency domain. All 3G and 4G wireless technologies use OFDM and FFT is an integral block of transceiver loop. In this paper three FFT architectures are designed that fall within the Cooley-Tukey class of algorithms. These FFT designs are targeted for OFDM applications especially in future generations of Software Defined Radio (SDR) systems. The FFT is performed on 64-point complex valued input samples with 16-bit precision. Each core is optimized for a combination of area, power, and speed. The design is targeted for a partially reconfigurable FPGA platform such as Xilinx Virtex-4 or above. The FFT cores have been simulated in Model Sim and synthesized using Xilinx ISE software. The cores can be readily downloaded on to target FPGA board to check for run time configurability. The performance evaluation of these cores show that they run at clock frequency of about 80MHz.

It is expected that multiple radio access standards and systems will coexist in the same environment beyond 3G. The superior re-configurability and re-programmability of software-defined radio (SDR) had made itself become the most promising technology to realize such a flexible radio system. Several research projects have involved in the development of SDR systems, but their efforts mainly focus on hardware design. A software framework that allows users, manufactures or operators to insert, remove, update and configure protocols, applications and hardware modules is also an essential part of a SDR system. Unfortunately, current commercial operating systems (OS) lack of fully supports of SDR features. In this paper, the impacts of SDR on the OS and the extension of the OS for a SDR system are investigated. Moreover, the design and implementation of a software framework based on a commercial on-the-shelf (COTS) OS are also presented.

AFF3CT is an open source toolbox dedicated to Forward Error Correction (FEC or channel coding). It supports a broad range of codes: from widespread turbo codes and Low-Density Parity-Check (LDPC) codes to more recent polar codes. The toolbox is written in C++ and can be used either as a simulator to quickly evaluate algorithms characteristics, or as a library in Software Defined Radio (SDR) systems or for other specific needs. Most of the decoding algorithm implementations aim at low latency and high throughput, targeting multiple Gb/s on modern CPUs. This is crucial in both simulation and SDR use cases: Monte Carlo simulations require high performance implementation as they commonly target the estimation of approximately 1012 bits. On the other hand, the implementations in real systems have to be very efficient to be competitive against dedicated hardware ones. Finally, AFF3CT emphasizes the reproducibility of state-of-the-art results by providing public references and open, modular source code.

ASoftware Defined Radio (SDR) system is a radio communication system, which uses software for modulation and demodulation of radio signals.In software defined radio (SDR) receivers, high-precision clock with very low jitter is required.It is intuitive to use only one fixed master clock.However, different wireless standards use different master clock rates.Under such circumstances, digital sample rate conversion (SRC) can be used as an important solution to provide different clock rates.The basic methods used in the SRC technology are decimation with down-sampling and interpolation with up-sampling, Down-sampling has to be preceded by filtering in order to avoid aliasing, while up-sampling must be followed by filtering to reject spectral images.In this paper, the design was implemented in FPGA using Verilog.The sampling rate conversion is performed by sampling the incoming signal and interpolating/decimating the signal to the desired value and then applying the low pass filter to eliminate aliasing.The sampling is done by digital mixer (Numerical controlled oscillator).The Interpolation/Decimation is performed by the CIC filter.FIR filter performs the low-pass filtering.The sampling rate converted value is given to the DSP processor for further processing.The projected application of the CSR_SDR are in GSM handset, CDMA handset and all the wireless applications.In this paper the functionality has been implemented, verified and checked using Verilog.

With the increasing demands of the data transmission system of information, wireless data transmission systems has been widely studied and applied. Especially the limited and specified environment, take the underground mine environment for example, has a high demand of flexibility. The paper describes the wireless video image data transmission system which is formed on the basis of DSP and RF chips, and provides the general systematic design and functional design. Furthermore, on this basis of the previous study, the paper has also completed the hardware and software design of the modules which consist two parts: data capture and compression modules; wireless data transfer and communication module. Regarding the further improvement of the use of DSP embedded technology in exploring the real-time wireless data transmission and communication system as well as its application level, there is a certain reference.

We present a reconfigurable GPU-based uplink detector for massive MIMO software-defined radio (SDR) systems. To enable high throughput, we implement a configurable linear minimum mean square error (MMSE) soft-output detector and reduce the complexity without sacrificing its error-rate performance. To take full advantage of the GPU computing resources, we exploit the algorithm's inherent parallelism and make use of efficient CUDA libraries and the GPU's hierarchical memory resources. We furthermore use multi-stream scheduling and multi-GPU workload deployment strategies to pipeline streaming-detection tasks with little host-device memory copy overhead. Our flexible design is able to switch between a high accuracy Cholesky-based detection mode and a high throughput conjugate gradient (CG)-based detection mode, and supports various antenna configurations. Our GPU implementation exceeds 250 Mb/s detection throughput for a 128×16 antenna system.

Machine Learning Modeling of GPS Features with Applications to UAV Location Spoofing Detection and Classification

We summarize the security necessary for software defined radio (SDR) systems, and propose a flexible structure for security systems on SDR. We introduce a new electronic commerce scheme for SDR that utilizes the ability of SDR to switch between different security algorithms for electronic commerce. We evaluate the performance of the cryptographic algorithms used in electronic commerce on various platforms including SDR systems, as basic research toward the implementation of SDR.

This paper presents a novel approach for mutual interference mitigation in automotive radars based on advanced waveform design by imposing time and frequency diversity to frequency modulated continuous wave (FMCW) chirp signal. Performance of the proposed waveform has been investigated using software-defined radio transceiver, and measurement results are provided. The system concept is validated by developed automotive radar channel model considering realistic 3D road traffic scenario using a ray-tracing tool. Theoretical analysis and simulation examples of mutual interference scenarios in automotive environment are provided to evaluate the effectiveness of the proposed method. Performance of both conventional FMCW waveform and proposed waveform under mutual interference environments has been provided for fair comparison. Results show that the proposed system is able to detect the targets of interest successfully while mitigates the false targets in mutual interference environments.

We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (network on chip) structure inside a FPGA. In the context of a SDR (software defined radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology for PR management regarding the timing performances obtained in a real implementation. PR timing is a key point to make SDR approach realistic. These results show that using PR, FPGAs combine the flexibility of SW (software) and the processing power of HW (hardware). This makes PR a tremendous enabling technology for SDR. These results are based on a new IP managing the ICAP component that allows a gain in time of a rate of 124 comparing to the provided OPBHWICAP. Moreover, we have integrated a methodology which can reduce significantly the bitstream size and consequently the reconfiguration duration. The results presented in this paper show that PR reconfiguration time can go downto a few tens of microseconds. This makes PR really attractive for SDR design or any other highly demanding real-time applications.

In this project, we propose an enhancement and analysis of transport control protocol friendly rate control (TFRC) for real-time data application (audio/video). Traditionally, real-time data transmission has been accomplished over the user datagram protocol (UDP). The challenging issues of using transport control protocol (TCP) are restrictive bandwidth and lagging. Additionally, it is widely known that TCP is ill-suited to real-time multimedia streaming application. Having known these issues, this project aims to study the possibilities for analysis and improvement of real-time data application using TFRC which is designed for long-lived streams. As known, there are many advantages of TFRC, which are congestion control and guaranteeing the required throughput. Therefore, this project explores and proposes the advantages of TFRC in transmitting and receiving real-time data which currently uses UDP. It is proposed that the investigation of TFRC in real-time data is conducted using simulation technique. During the simulation, the developed model is representing the real-time application for analyzing the performance of modified TFRC. The simulation study of this project is to analyze and evaluate some of restraint issues for real-time data application to use TFRC. As a solution, a few suggestions are discussed to overcome stated problem and make comparison and evaluation, which are aimed to get results about better performance between enhanced TFRC and UDP in terms of streaming real-time data.

Software-defined radio (SDR) is an emerging technology that offers various advantages over conventional radio designs. The SDR approach uses a common hardware platform, programmed by software modules and firmware, to support many communications standards and operating frequencies. The technology is being promoted by the US Department of Defense to replace tens of thousands of single-protocol, single-purpose radios with a common platform. Military and public safety organisations worldwide are also considering this technology to solve interoperability problems enabling, for example, police and firefighters to easily communicate in the field. In addition, the commercial wireless industry views SDR as a means of reducing development cost and time to market. To fully realize SDR’s promise of an all-encompassing communications device capable of transmitting and receiving over a very wide frequency range requires special attention to the radio frequency (RF) transceiver. Although it is relatively easy to use conventional electronics to build SDRs operating at up to 6GHz, it is increasingly difficult to do so at higher operating frequencies. It needs a hardware platform capable of operating up to about 60GHz to take full advantage of the SDR concept. Ideally, the SDR hardware platform has a continuouslytunable source to act as a local oscillator. It should be possible to modulate this source in any format, perform signal conditioning, and distribute the signal: either by wireless transmission or over an optical network. The prospect of using conventional electronics to develop a commercially-viable source with these properties is limited, so it may be necessary to find another approach. Optical technology can emulate many of the functions normally associated with RF reception and transmission. For example, it is possible to generate microwave signals optically over a very large frequency range—from MHz to THz—using heterodyne techniques such as optical injection locking, optical phaselocked loops, and nonlinear up-conversion. The electrical RF signal is generated by shining two optical inputs, separated by the desired microwave frequency, on to a square-law photodetector that acts as a mixer and generates their beat frequency. In general, when no phase or frequency control is applied, the phase noise of the microwave signal is approximately equal to the sum of the optical linewidths. The key to reducing this typicallyMHz linewidth down to values that are more practical for a communications system is to ensure that the phases of the optical signals are highly correlated. If they are, a very narrow RF linewidth can be achieved, even from large-linewidth optical sources. A carrier is of limited use in a communication system without some form of encoded information. A laser source can be modulated by inserting a baseband optical modulator in the optical path, or by other means. The modulation formats are varied and may act on the frequency, amplitude, or phase of the signal. In general, the bandwidth of the modulator/demodulator is dictated by the format of the protocol or the radio-spectrum channel allocation and is relatively modest, since the high-frequency carrier is already optically generated. This means that digital demodulation can be done directly by the computer, after optical down-conversion, to make it easier to interface with the SDR software. Both the receiver and transmitter need RF filtering for signal conditioning. Techniques for electrical filtering in the optical domain have been examined extensively, but the all-optical microwave filters proposed to date are primarily based on incoherent manipulation of optical carriers with only positive taps. This approach can only create low-pass filters. Many applications, including SDR systems, need bandpass and flat-top filters as well. To overcome this limitation, Yao et. al. recently reported a way to build an all-optical microwave bandpass filter with a simple structure.