Real-Time Average Junction Temperature Estimation for Multichip IGBT Modules With Low Computational Cost

Accurate junction temperature prediction in multichip insulated gate bipolar transistor (IGBT) modules is paramount for ensuring the reliability and efficiency of power electronic systems. Given the high integration density and intricate thermal coupling among multiple chips, developing an efficient method for junction temperature estimation is essential for IGBT power modules. This article presents a novel digital twin-based method for accurately monitoring junction temperature in multichip power modules. A digital twin modeling framework of IGBT testing is first presented. Subsequently, the current-sharing behavior in multichip power modules is analyzed and systematically modeled. Power loss calculations based on the current balancing are then performed, complemented by finite element simulations to derive the temperature distribution and heat-dissipation characteristics of the module. Leveraging this foundation, a convolutional neural network (CNN)-enhanced digital twin approach is proposed to achieve real-time temperature prediction. The effectiveness and accuracy of the proposed method are rigorously validated through a double-pulse test (DPT) platform and reactive aging experiments. The results demonstrate that this framework offers a highly efficient solution for real-time junction temperature monitoring and thermal management in multichip IGBT modules.

This paper proposes a novel method for optimizing the Cauer-type thermal network model considering both the temperature influence on the extraction of parameters and the errors caused by the physical structure. In terms of prediction of the transient junction temperature and the steady-state junction temperature, the conventional Cauer-type parameters are modified, and the general method for estimating junction temperature is studied by using the adaptive thermal network model. The results show that junction temperature estimated by our adaptive Cauer-type thermal network model is more accurate than that of the conventional model.

Research on IGBT junction temperature model based on united-parameters

Infrared (IR) techniques can accurately measure temperatures with high spatial resolution, on the order of a few microns resolution. In microelectronics, however, a device’s hot spot, the junction temperature, is a small fraction of a micron. Accurate prediction of junction temperature is critical for reliability and thermal management. This paper presents an accurate closed form model for the junction temperature as a function of device geometry. Based on knowledge of the temperature profile it is possible to reverse the averaging inherent in the IR measurement and obtain the junction temperature accurately based on IR microscopy. This paper illustrates this approach for the case of field effect transistors (FETs) and applies it to several actual measurements.

The design of a power converter must guarantee that the operating junction temperatures thetavj of all devices do not exceed their limits under all specified operating conditions. Usually, this is ensured by a simulative or analytical junction temperature estimation based on simple electrical and thermal models and semiconductor datasheet values. This paper discusses the difficulties and quantifies the limitations of this approach on the example of a three-level neutral point clamped voltage source converter (NPC VSC) with insulated gate bipolar transistors. The calculations are compared to the results of direct junction temperature measurements with an infrared camera. The paper also provides the experimental proof for the unequal loss and junction temperature distribution in the three-level NPC VSC

There are challenges to the reliability evaluation for insulated gate bipolar transistors (IGBT) on electric vehicles, such as junction temperature measurement, computational and storage resources. In this paper, a junction temperature estimation approach based on neural network without additional cost is proposed and the lifetime calculation for IGBT using electric vehicle big data is performed. The direct current (DC) voltage, operation current, switching frequency, negative thermal coefficient thermistor (NTC) temperature and IGBT lifetime are inputs. And the junction temperature (T j) is output. With the rain flow counting method, the classified irregular temperatures are brought into the life model for the failure cycles. The fatigue accumulation method is then used to calculate the IGBT lifetime. To solve the limited computational and storage resources of electric vehicle controllers, the operation of IGBT lifetime calculation is running on a big data platform. The lifetime is then transmitted wirelessly to electric vehicles as input for neural network. Thus the junction temperature of IGBT under long-term operating conditions can be accurately estimated. A test platform of the motor controller combined with the vehicle big data server is built for the IGBT accelerated aging test. Subsequently, the IGBT lifetime predictions are derived from the junction temperature estimation by the neural network method and the thermal network method. The experiment shows that the lifetime prediction based on a neural network with big data demonstrates a higher accuracy than that of the thermal network, which improves the reliability evaluation of system.

Thermal loading of Insulated Gate Bipolar Transistor (IGBT) modules is important for the reliability performance of power electronic systems, thus the thermal information of critical points inside module like junction temperature must be accurately modeled and predicted. Usually in the existing thermal models, only the self-heating effects of the chips are taken into account, while the thermal coupling effects among chips are less considered. This could result in inaccurate temperature estimation, especially in the high power IGBT modules where the chips are allocated closely to each other with large amount of heat generated. In this paper, both the self-heating and heat-coupling effects in the of IGBT module are investigated based on Finite Element Method (FEM) simulation, a new thermal impedance model is thereby proposed to better describe the temperature distribution inside IGBT modules. It is concluded that the heat coupling between IGBT and diode chips strongly influence the temperature distribution inside IGBT module, and this effect can be properly modeled/predicted by the proposed thermal impedance model.

As the power density of press-pack insulated gate bipolar transistor (PP-IGBT) modules increases, establishing a thermal analysis model to provide thermodynamic information for PP-IGBT modules under service conditions is crucial for reliability design and thermal management. Existing thermal models, such as one-dimensional (1D) lumped RC thermal network models, have limitations in terms of accurately predicting the thermal behavior of PP-IGBT modules; i.e., the effect of thermal contact resistance degradation resulting from contact surface damage on the junction temperature is not considered. This study proposes an improved 1D lumped RC thermal network model for PP-IGBT modules. Following different numbers of power cycles, the transient PP-IGBT module thermal impedances were measured, and the evolution of the thermal contact resistances at each contact surface was obtained. Then, thermal contact resistance degradation was introduced into the RC thermal network model. We compared the calculated junction temperature results with the measured results to verify the proposed model. The model enables a more accurate prediction of the junction temperature of PP-IGBT modules under long-term service conditions.

During the operation of an LED array, its thermal and optical performances are always not equal to the superposition of the individual LED's characteristics because of a significant thermal coupling effect between the arrays. Based on this, this paper proposes an electrical–photo-thermal model, with considering both junction temperature and luminous flux, to predict the both the thermal and optical performances of LED arrays operated under different currents, case temperatures, and lighting methods. The junction temperature and luminous flux of a single LED operating under different driving currents and case temperature conditions are firstly collected to establish the luminous flux response surface model of a single chip. Then it is used to predict the luminous flux of an array, whose junction temperature is predicted using both thermal coupling matrix (TCM) and numerical models. Experiments verify the luminous flux of the LED array under different operation conditions and show that the proposed electrical–photo-thermal modeling can be used to predict the thermal and optical parameters of LED arrays with 95 % accuracy. Thus, it is effective for the fast prediction of the junction temperature and luminous flux of large LED systems with array structures, i.e. intelligent automotive lightings and displays.

The junction temperature of LEDs is important for its life, reliability and efficacy. The thermal resistance measurement can be implemented to obtain the junction temperature of a single-chip LED in different power consumptions and different environment temperatures. However, for the multichip applications such as Chip-on-Board (COB), multi-color and high-voltage LED packaging etc., only the average junction temperature can be obtained by the traditional steady thermal resistance measurement. In this paper, a thermal resistance matrix with thermal coupling factor is proposed to obtain the junction temperature of each chip in a multi-chip LED with different chip powers. In the case study, each element of the 4×4 thermal resistance matrix of a Red-Green-Blue-White (RGBW) four-chip LED is tested by a transient thermal tester (T3ster) to investigate the thermal coupling of chips one another. In addition, the thermal distribution of the LED package was analyzed by finite element analysis (FEA) simulation for comparison. It is shown that the thermal resistance matrix is effective for evaluation of junction temperature of each chip in the multi-chip LED package with a discrepancy less than 2.5% from measurement.

Temperature sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{j}$ </tex-math></inline-formula> ) detection and prediction of power devices, especially the switching parameter. In this article, the voltage-rise time and its loss during the turn-off process are used as the TSEP index for the detection of junction temperature because of the coupling relationship with the maximum junction temperature. In addition, the effect of junction temperature on the current-fall time and its loss is compared. The theoretical analysis is verified by SABER simulation and H-bridge inverter circuit platform. It is established that the model based on voltage-rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\mathrm {rv}}$ </tex-math></inline-formula> ) and voltage-rise loss ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\mathrm {rv}}$ </tex-math></inline-formula> ) is a viable model with good linearity, fixed sensitivity, and offers nondestructive insulated gate bipolar translator (IGBT) junction temperature extraction.

Capacitance and Insulated gate bipolar transistor (IGBT) junction temperature are two critical healthy parameters for modular multilevel converters (MMC) sub‐modules (SMs) condition monitoring. This paper proposes an integrated monitoring method for capacitance degradation and IGBT junction temperature variation. By measuring multiple characteristics of the same port voltage, the capacitance and the junction temperature can be obtained simultaneously, which greatly simplifies the measurement unit required for condition evaluation and realizes the submodule‐level condition monitoring at a lower cost. The capacitance is characterized by voltage changes during capacitor discharging and the junction temperature is monitored by capacitor voltage overshoot (peak value) during IGBT turn‐off. Theoretical analysis and experimental results verify the effectiveness of the proposed method and articulated the influence of load current, SM capacitor pre‐discharge voltage, and junction temperature. Moreover, an online data‐acquisition circuit for time‐specific capacitor voltage characterization is devised.

The heat transfer of power devices has the characteristics of multitimescale. However, the traditional thermal network model is difficult to predict the temperature information of power devices at multitimescale accurately. This article proposes a multitimescale thermal network model for power devices, with metal-oxide-semiconductor field-effect-transistor ( <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> ) as an example. First, we establish a finite-element model for temperature calculation of power devices and then reduce the order of the finite-element model based on the proper orthogonal decomposition algorithm. The reduced-order model is converted into an equivalent circuit model by the node voltage method and integrated into the circuit simulation software. To demonstrate its general applicability, this article also establishes thermal network models for both insulated gate bipolar transistor (IGBT) and SiC <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfet</small> devices, and validates the multitimescale thermal network models through ANSYS/transient thermal software and experiments. The temperature calculation results of the three power devices all indicate that the proposed multitimescale thermal network model can calculate the temperature of power devices faster than the ANSYS/transient thermal model and has less than 5% error under test conditions. This article is accompanied by a video demonstrating a comparison of the computational speed of the multitimescale thermal network model with a finite-element model. Finally, a case study of junction temperature calculation in a buck converter is presented to illustrate the application method of the thermal network model.

Performance of power dissipation on semiconductor module for different configuration of heat SINK with thermal pad

This paper presents a performance analysis of grid connected SPV system for different maximum power point tracking (MPPT) algorithms. The detailed mathematical model of grid connected three-phase solar photovoltaic (SPV) system with parametric model of SPV cell, thermal modelling and switching loss calculation of switching devices are discussed. The performance evaluation has been carried out for perturb-and-observe (P&O) and incremental conductance (IC)-based MPPT algorithms for various outputs of the SPV array, in terms of energy injected to grid, switching losses, junction temperature and sink temperature, for switching in the DC-DC boost converter. The results validated the effectiveness of the MPPT algorithm in increasing SPV output energy, decrease in the switching losses, junction and sink temperature. The results show that IC method is slightly better to P&O method in energy injected to the grid with lower switching losses, junction and sink temperature.