Prediction of submicron junction temperatures in microelectronics using IR techniques

The junction temperature of the insulated gate bipolar transistor (IGBT) modules is a vital parameter for the reliability of the power electronic system. For effective thermal management, it is necessary to estimate junction temperature in real time. However, existing thermal models have limitations to achieve fast temperature prediction for multichip IGBT modules. In this study, we investigate the real-time junction temperature prediction for multichip IGBT modules with low computational cost. According to the power module' structure, an average 2D thermal model with physical significance is proposed to predict the virtual junction temperature for multichip IGBT modules, which can be extracted from finite element model based on the least square method. To further improve the computational efficiency, a temperature predictor based on the staggered cycle-by-cycle calculation method is proposed and its prediction error under various extreme operation conditions is analyzed by enumeration method. Finally, the comprehensive experimental results verify the effectiveness of the proposed average thermal model and junction temperature prediction method.

Accurate junction temperature prediction in multichip insulated gate bipolar transistor (IGBT) modules is paramount for ensuring the reliability and efficiency of power electronic systems. Given the high integration density and intricate thermal coupling among multiple chips, developing an efficient method for junction temperature estimation is essential for IGBT power modules. This article presents a novel digital twin-based method for accurately monitoring junction temperature in multichip power modules. A digital twin modeling framework of IGBT testing is first presented. Subsequently, the current-sharing behavior in multichip power modules is analyzed and systematically modeled. Power loss calculations based on the current balancing are then performed, complemented by finite element simulations to derive the temperature distribution and heat-dissipation characteristics of the module. Leveraging this foundation, a convolutional neural network (CNN)-enhanced digital twin approach is proposed to achieve real-time temperature prediction. The effectiveness and accuracy of the proposed method are rigorously validated through a double-pulse test (DPT) platform and reactive aging experiments. The results demonstrate that this framework offers a highly efficient solution for real-time junction temperature monitoring and thermal management in multichip IGBT modules.

During the operation of an LED array, its thermal and optical performances are always not equal to the superposition of the individual LED's characteristics because of a significant thermal coupling effect between the arrays. Based on this, this paper proposes an electrical–photo-thermal model, with considering both junction temperature and luminous flux, to predict the both the thermal and optical performances of LED arrays operated under different currents, case temperatures, and lighting methods. The junction temperature and luminous flux of a single LED operating under different driving currents and case temperature conditions are firstly collected to establish the luminous flux response surface model of a single chip. Then it is used to predict the luminous flux of an array, whose junction temperature is predicted using both thermal coupling matrix (TCM) and numerical models. Experiments verify the luminous flux of the LED array under different operation conditions and show that the proposed electrical–photo-thermal modeling can be used to predict the thermal and optical parameters of LED arrays with 95 % accuracy. Thus, it is effective for the fast prediction of the junction temperature and luminous flux of large LED systems with array structures, i.e. intelligent automotive lightings and displays.

Temperature sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$T_{j}$ </tex-math></inline-formula> ) detection and prediction of power devices, especially the switching parameter. In this article, the voltage-rise time and its loss during the turn-off process are used as the TSEP index for the detection of junction temperature because of the coupling relationship with the maximum junction temperature. In addition, the effect of junction temperature on the current-fall time and its loss is compared. The theoretical analysis is verified by SABER simulation and H-bridge inverter circuit platform. It is established that the model based on voltage-rise time ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$t_{\mathrm {rv}}$ </tex-math></inline-formula> ) and voltage-rise loss ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$E_{\mathrm {rv}}$ </tex-math></inline-formula> ) is a viable model with good linearity, fixed sensitivity, and offers nondestructive insulated gate bipolar translator (IGBT) junction temperature extraction.

As the power density of press-pack insulated gate bipolar transistor (PP-IGBT) modules increases, establishing a thermal analysis model to provide thermodynamic information for PP-IGBT modules under service conditions is crucial for reliability design and thermal management. Existing thermal models, such as one-dimensional (1D) lumped RC thermal network models, have limitations in terms of accurately predicting the thermal behavior of PP-IGBT modules; i.e., the effect of thermal contact resistance degradation resulting from contact surface damage on the junction temperature is not considered. This study proposes an improved 1D lumped RC thermal network model for PP-IGBT modules. Following different numbers of power cycles, the transient PP-IGBT module thermal impedances were measured, and the evolution of the thermal contact resistances at each contact surface was obtained. Then, thermal contact resistance degradation was introduced into the RC thermal network model. We compared the calculated junction temperature results with the measured results to verify the proposed model. The model enables a more accurate prediction of the junction temperature of PP-IGBT modules under long-term service conditions.

Research on IGBT junction temperature model based on united-parameters

Evaluation of IGBT thermo-sensitive electrical parameters under different dissipation conditions – Comparison with infrared measurements

Gallium nitride high-electron-mobility transistors (GaN HEMTs) are critical for high-power applications like AI power supplies and robotics but face reliability challenges due to increased dynamic ON-resistance (RDS_ON) from electrical and thermomechanical stresses. This paper presents a novel self-calibrating temperature-sensitive electrical parameter (TSEP) model that uses gate leakage current (IG) to estimate junction temperature with high accuracy, uniquely addressing aging effects overlooked in prior studies. By integrating IG, aging-induced degradation, and failure-in-time (FIT) models, the approach achieves a junction temperature estimation error of less than 1%. Long-term hard-switching tests confirm its effectiveness, with calibrated RDS_ON measurements enabling precise remaining useful life (RUL) predictions. This methodology significantly improves GaN HEMT reliability assessment, enhancing their performance in resilient power electronics systems.

In this work, a new and improved SFM is presented. This SFM can measure many variables such as the individual dynamic and active temperature regulation of the sample and the cantilever, miscellaneous friction modes, x-, y-, z- linearization and an increased scan speed, simultaneous with high spatial resolution. The scan width is also laterally extended to 1 millimetre by 1 millimetre. This extension of the lateral scan range requires a larger tilt compensation. Therefore, the z-scanner has a range of more than 300 µm. Summary In this thesis, a novel scanning force microscope was presented. Other than the large scan range of approximately 1000 µm by 1000 µm, the thermal guidance of the cantilever and sample is the most labour-intensive component of the microscope. Detailed construction of the cantilever holder and sample holder, light beam guidance for the normal and lateral forces, the positioning and scan unit, and ECU, control software and communication software have been discussed. The entire microscope was constructed as symmetrically as possible using mechanical construction to avoid thermal drift. For thermal measurements and thermally assisted friction measurements, a concept for separately heating the cantilever holder and the sample holder was discussed. A simulation on the cantilever holder showed that a temperature difference of 150°K could be reached after 40 s and that the cool down cycle took only 38 s, without any disturbance of the nearest piezo. The same analysis was performed for the sample holder. Only the junction temperature for unknown samples and the temperature behaviour of these samples was calculated. After 15 s of heating, the junction reached 150 °K above the ambient temperature. The thermal path to the next piezo element is more critical than the one for the cantilever holder setup, therefore, the thermal management is more complex. However, the analysis has shown a maximum rise of 32 K above the ambient temperature at the piezo element for the heating and cooling scenario described above. For the beam deflection setup, a single-mode glass fibre supply of the laser light beam was used. A special grinding technique was used to form fibre tips, which can be short-duration fused to form a small lens for pre-focusing the light beam (two patents have been submitted). A sample setup showed that the self-assembled laser beam has a diameter of approximately 60 µm. With 10 µW of light on the 4Q-PD using a standard cantilever, the electronics produced a displacement equivalent to the noise of approximately 0.1 nm with a 10 kHz low-pass filter. With the beam deflection system introduced here, even the first and second resonances, in addition to the basic one, were observable. The torsional basic mode and its first harmonic were also observed. The Z-drive was separated into low, mid-range and high-frequency components. This separation aids with the thermal management of the microscope to avoid and/or remove unwanted thermal heating in areas of the system where mechanical drift disturbs the scanning force measurements. The hydraulically driven low frequency Z-component fulfils this requirement. A European patent has been granted for the hydraulic cylinder design. While linearization in x-, y-, and z-direction is always desirable, it is a necessity for the scan range of the microscope introduced here. Each scan range could be assembled with a specially adapted linearization unit (fibre bundle and mirror) as the linear behaviour of each linearization unit is proportional to the numerical aperture of the guiding fibres. Finally, the ECU and the control, communication and visualisation software were presented. The centrepiece of the ECU is a Texas Instruments 6711 floating point DSP. This unit features the real-time capability that is necessary to drive such a microscope. The DSP communicates via a serial, insulated interface (FireWire®) with the PC in burst mode, while collecting data from the sensor channels in strict, fixed time-slices. Again, the data channels have to be precise and very fast due to the large scan range, to keep the scan times in a manageable regime. Six channels have 16 bit resolution at 1 MSPS, four channels have 16 bit resolution at 500 kSPS, and eight channels have 16 bit resolution at 250 kSPS. One time-slice was also used up to 128 times for multiplexing pre-selection for one arbitrary channel, which can be used to detect slowly changing signals. At this sample rate, a meander-shaped scan line could be achieved. Different types of deceleration and acceleration behaviour were calculated to obtain the largest possible linear scan range, resulting in cubical behaviour during deceleration and acceleration for even the smallest disturbance in the linear scan regime. The mixer electronics were designed with offset and zoom capabilities. This results in linear DAC sample steps within the chosen region, independent of the user-chosen region of interest (angle and size).

III-Nitrides promise to offer high-frequency power amplifiers at higher power densities. This is attractive for realizing device platforms for 5G and beyond. It also enables integrating Si-based electronics to complement functionalities. However, to obtain the full potential of III-Nitrides one must operate these transistors at higher power densities, for which thermal management is crucial.Due to the continuous need for higher performance in various applications ranging from DC to W-band frequencies, semiconductor devices are pushed to higher power densities. This results in a higher junction temperature owing to the Joule heating in the channel resulting in device performance degradation and premature failure. Using devices based on wide-bandgap (WBG) semiconductors such as Gallium Nitride (GaN) and Gallium Oxide (GaOx) with a larger critical electric field and high-temperature tolerance, one could increase the power density. However, in order to increase the output power to the levels that is promised by these wide bandgap materials, junction temperature reduction through device-level cooling is critical. We are actively researching thermal management at device, circuit and packaging level using synthetic polycrystalline (PC) diamond. PC-diamond, at an appropriate grain size offers a TC is higher than any competing thermal vias with metals without interfering the electrical performance. Over the past 5 years we have demonstrated the potential of integrating diamond with GaN and recently achieving a record low diamond/GaN thermal boundary resistance (TBR) along with a relatively high diamond thermal conductivity (TC). This remarkable thermal performance was be achieved by maintaining the electrical performance, as demonstrated by the unharmed channel charge and mobility results.There are two key requirements for thermal management using heat spreading from the channel: first, a low thermal boundary resistance (TBR) between the hot spot in the channel and the heat spreader is required (in this study between GaN channel and diamond). Second, a low thermal resistance path to the heat-sink is crucial from the diamond layer which is directly proportional to diamond’s thermal conductivity (TC). In collaboration with Univ of Bristol, we have reported a TBR of ~3 m2K/GW, to date, known to be the lowest reported TBR for GaN HEMT technology. Diamond-GaN TBR depends strongly on the interface smoothness and the thickness of interfacial Si3N4 layer. A thinner Si3N4 resulted in lower TBR and allowed superior phonon coupling from the channel to the spreader. We have also measured a remarkably high TC for a 2 μm-thick diamond layer yielding over 650 W/m.K. The diamond grains are near isotropic in shape that allows excellent in-plane and cross-plane thermal conductivity. Achieving high TC within a thin film of diamond, grown heterogeneously, underscores the importance of our technique, since it reduces the residual stress when integrating with different materials that involves many thin layers like GaN/AlGaN HEMT epi-layers.β-Ga2O3 is an emerging ultra-wide bandgap material showing promises for both power and RF devices. However, the material’s low thermal conductivity poses to be a challenge for efficient power delivery (at any frequencies). PC diamond was successfully grown on (‾¯201)β-Ga2O3 using proper nucleation technique and thermal characterizations were conducted. A thermal conductivity (diamond + nucleation) and thermal boundary resistance at the diamond/β-Ga2O3 interface of 110 ± 33 W/mK and 30.2 ± 1.8 m2K/GW, respectively were measured.Our current results demonstrates a very promising roadmap for wide bandgap semiconductors via diamond integration.

The junction temperature is important for condition monitoring, thermal management, and the operating-life-prediction of power semiconductor device. The junction temperature fluctuation, in particular, is a leading cause of IGBT module failure. Thus, extracting the junction temperature is vital to assess the reliability of IGBT module. This section summarizes the junction temperature extraction method and introduces a measurement method that uses the switching characteristic of the device. Because the lifetime prediction needs to handle a large amount of mission profile data, a numerical junction temperature calculation method, which computes with high speed, is also introduced in this section.

The demand for energy resources to improve our quality of life continues to increase. However, the prices of Fossil Energy keep going up and the resources are limited. Therefore, more and more reusable energy resources are being developed. The foremost among these reusable energy resources is solar energy. A solar cell, powered by solar energy, uses semiconductors to transform light into electric power. The difference in structure between high-concentration photovoltaic (HCPV) solar cell and traditional solar cell is the usage of concentrated-light module to enhance the optic-electric transition efficiency. In general, under concentrated-light operation condition, the device temperature rises with increasing light concentration ratio. In other words, due to a decrease in open-circuit voltage as a function of increasing temperature, the system output power or energy-conversion efficiency decreases with the increasing temperature of the cell incorporated within the system. Therefore, thermal management has been an important issue for the package of a high-concentration photovoltaic solar cell. In this research, we first established a detailed finite element model of the HCPV solar cell package as a benchmark using ANSYS® finite element analysis program. The established finite element model can simplify and quickly resolve the thermal management problem of the HCPV solar cell package. We also performed Infrared (IR) thermography measurement experiment in order to validate the finite element model. After validation of the experimental results, we analyzed the variation of thermal performance under different design parameters of the HCPV solar cell package. Based on the simulation results of different design parameters, it can be found that the thickness of the heat sink plate plays important roles in the thermal management of the HCPV solar cell package, which indicates that the thicker the thickness of the aluminum plate, the lower the junction temperature of the HCPV solar cell package. Furthermore, the thermal conductivity of the test board and solder paste has a light effect to reduce junction temperature. The other result shows the capability of a protection gel not only to protect the die surface and wire bond but to also reduce cell temperature under a highly concentrated light condition.

Dynamic high temperature operating life test methodology for long-term switching reliability of GaN power devices

Modern high-performance processors are embedded in portable electronics, such as smartphones, self-driving automobiles, and augmented reality wearable. These computing platforms provide real-time direction navigation, high definition video entertainment, real-time sensing and control. One of the major performance limiting factors in these platforms is the poorly designed thermal solution to prevent overheating at the processor transistor junction and at the platform surface. The former limits the maximum operating temperature of transistors to guarantee reliability and lifetime whereas the latter limits the maximum platform surface temperature to ensure user ergonomic comfort. To design effective cooling solutions for high-performance, multi-layer, multi-processor platforms, an accurate and detailed platform level temperature model is needed. In this work, we present a detailed finite volume model to predict the temperature behavior of a tightly packaged, high-performance portable platform, from the system level down to the processor architecture level. We first characterize the thermal response of real-world, representative mobile workloads and perform parametric studies to predict the processor junction and platform surface temperature based on the properties of the platform. We observe that thermal hot spots are sensitive to workload computation characteristics. In particular, for mobile workloads, such as web browsing, computations often occur in short time burst, leading to instantaneous power spikes. This results in temperature spikes as thermal hot spots. To mitigate the thermal issue, modern systems implement dynamic voltage and frequency scaling during high performance and high power scenario to prevent cores from overheating. We validate the proposed temperature model used to predict the maximum temperature at the processor chip and at the platform surface, with measurements from the embedded temperature sensors and an infrared camera. The temperature prediction accuracy for hot spots on the processor chip and on the platform surface is demonstrated to be higher than 90%. With the tool, we show that the physical construction (such as air gaps and material properties) and the floor plan of the multi-layer platform have a profound effect on the system temperature behavior. As the air gap between the different layers of the computing platform increases, the processor temperature rises significantly. Also there exists an optimal thickness setting of the air gap for platform surface thermal spreading. We hope the detailed characterization results, the developed temperature prediction tool, and the insights presented in the paper can motivate advanced thermal management solution for high-performance embedded platforms in the years to come.

The channel temperature of Gallium Arsenide (GaAs) devices was quantitatively measured using scanning thermal microscopy (SThM), which is a variation of atomic force microscopy (AFM). The temperature of the devices was also characterized by infrared (IR) imaging and thermal modeling. The measured SThM temperature values were close to the calculated values from the model, and were higher than those found by IR, as predicted. In contrast to most published AFM results which have reported only qualitative and indirect semi-quantitative thermal information about the sample, the results presented here can be used directly to determine accurately the device-temperature. These results are useful to the reliability community in that they help to predict a more accurate semiconductor device lifetime. By careful calibration of an AFM thermistor probe tip, a quantitative temperature measurement of the channel temperature of the GaAs PHEMTs and MESFETs can be made. The result of the measurement can be substantiated by applying a suitable thermal calculation, such as the Cooke model. A secondary measurement technique, such as IR microscopy, can also be useful in providing further information about the thermal response of the device. Published results using AFM techniques have been unable to determine the channel temperature quantitatively. The method in this paper applies to other types of electronic devices for which the channel (or junction) temperature can be probed from the top surface of the device.