Real-time visual content description system based on MPEG-7 descriptors

Real-time shape description system based on MPEG-7 descriptors

This study develops a highly reliable real-time visual tracking system capable of tracking a moving target in cluttered environment. The proposed system architecture can be divided into three main parts - the target detector, the target information extractor and the target tracker. The first part detects any moving object in the image, using the moving edges technique. Next, by integrating the information from the target detector and the attractable snake model, the second part automatically extracts the target's contour, illumination and color information to enable the target to be tracked. Finally, by adopting a new hybrid matching method, the third part enables the system to continuously track the target with great robustness and adaptability. Notably, this hybrid matching method incorporates the template matching method with a modified contour matching method. Furthermore, the visual tracking system developed in this study is established on a low-cost commercial camera platform, which can be controlled by a personal computer through an RS232 serial port. Finally, several experiments, including object tracking and human head tracking, are conducted to verify the robustness of the tracking system.

Among web-based systems being widely used now, there are so many systems which are still using an user-level access control method. By successfully applying role-based access control(RBAC) to web-based application systems, we can expect to have an effective means with reinforced security for Internet-based systems. In order to apply RBAC to web-based application systems, we should come up with a system architecture for it. I proposed a system architecture which is needed to apply RBAC to web-based application systems. The proposed system architecture is largely composed of system composition and system functioning. For details, firstly, a certificate used by RBAC is specified. Secondly, a system architecture using a user-pull method is proposed and overall system components are mentioned with a role server being centered. Then, I showed how the system architecture can work to carry out RBAC on web-based application systems. Lastly, the analyses on the proposed system architecture are described for the purpose of proving its feasibility.

The application of assistive robots is increasing in the day-to-day life. Assistive robotic systems are useful in the different domains ranging from medical, domestic and other indoor fields. Based on the utility, several applications of the assistive robots can be thought of. This paper outlines the steps involved in design and simulation of a mobile robot platform for an indoor office environment. The different phases of the development are discussed. The proposed system architecture is based on the real time navigation with dynamic obstacle avoidance in an indoor environment. For this purpose, 3D vision sensor-based navigation architecture is discussed. The target application for the robot model is object transfer from one location to other. The hardware and software architecture needed for the development of the model are presented in detail.

Describes a parallel-processor LSI chip (the Integrated Memory Array Processor, IMAP) and a compact real-time vision system (RVS-2). The IMAP integrates 64 8-bit processors, which operate in a SIMD manner, and 2-Mbit image memory on a single chip, and has peak performance of 3.84 GIPS. The RVS-2 consists of 8 IMAPs, a video interface, a control LSI chip (the Real-time Vision System Controller, RVSC) and a host workstation. RVSC is a 16-bit processor which carries out global data operations as well as providing an instruction stream to IMAP processors. In the RVS-2 system, the IMAP processors accomplish data-parallel operations, the RVSC applies global data operations to the results, and the host workstation carries out higher-level recognition tasks using the results obtained by the IMAPs and the RVSC. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing is carried out in 0.1 to 0.7 ms, which is 50 to 300 times faster the video rate.

Mobile Cloud Computing (MCC) is a developing technology that assists in improving the quality of the mobile services. Since the increase in mobile resources, the researchers have taken the initiative to take into contemplation resource sharing among heterogeneous mobile devices. Therefore, to design a system architecture for mobility models and resource sharing are key issues that require utmost efforts to be solved to achieve anticipated objectives. Therefore, keeping in view the desired goals, in this paper, we present a system architecture based on the hierarchical resource sharing mechanism for MCC. The proposed system architecture is divided into three domains, such as Global Cloud Server (GCS), Local ISP Server (LIS), and Gateway Server (GWS). Also, the novel paradigm for minimizing the delay in the network based on deploying Foglets at each proposed algorithm of clustering mechanism is also present. Moreover, the fuzzy rule-based scheme is proposed to eliminate the inappropriate foglets before deciding an optimal foglet for handover. A foglet selection scheme is developed based on the Technique for Order of Preference by Similarity to Ideal Solution (TOPSIS) decision mechanism. Various parameters such as delay, jitter, Bit Error Rate (BER), packet loss, communication cost, response time, and network load are considered for selecting an optimal network. To check the feasibility and performance of the proposed system architecture, the mobility scenario is considered with a different speed of a mobile node ranging from very high to very low. The simulation results and an analytical model are compared with existing scheme for foglet selection by a mobile node. From the analysis and discussion, it is shown that the proposed system architecture helps in minimizing handover delay, packet loss, average queuing delay, and device lifetime. in a network.

MPEG-7 is a promising standard for the description of multimedia content. Today, more and more multimedia applications based on MPEG-7 descriptions have been set up for research, commercial and industrial applications. Therefore, an efficient storage solution for large amounts of MPEG-7 descriptions is certainly desirable. However, few existing works focus on a comprehensive MPEG-7 descriptions management system. Although the MPEG-7 descriptions are also the XML documents, the current database solutions for XML documents do not fulfill all the requirements for the management of MPEG-7 descriptions. The goal of this thesis is to investigate the MPEG-7 descriptions storage solution and present the implementation of an MPEG-7 descriptions management system: IXMMS, which is based on RDBMS and ORDBMS. IXMMS is a novel XML storage solution to overcome the problems in the current XML storage solutions for the management of MPEG-7 descriptions. The design of IXMMS pays attention to both multimedia information exchange and multimedia data manipulation. IXMMS introduces two separate databases, one to store MPEG-7 descriptions from the XML perspective, and the other for the low-level multimedia content within the MPEG-7 descriptors. Thus, IXMMS supports the management of MPEG-7 descriptions and MPEG-7 information exchange not only from the XML perspective, but also from the multimedia perspective, and its features can reach the most critical requirements for the MPEG-7 documents storage and management.

In this paper we propose a system architecture that extends the current state-of-the-art in computational visual attention by incorporating the biological concept of ventral attention. According to recent findings regarding the neurobiological foundations of attention, there exist two separate but interacting attention systems in the human brain: the dorsal attention system and the ventral attention system. As opposed to the well-known computational concepts of bottom-up and top-down saliency, which both correspond to the dorsal attention system, the ventral attention system is sensitive to behavior-relevant stimuli that are unexpected (i.e. not top-down salient), independent of their perceptual saliency (bottom-up saliency). This results in a dynamic interplay between top-down saliency, bottom-up saliency and ventral attention in the proposed system architecture, enabling the system to redirect its focus of attention to important stimuli while being absorbed in a task, even if their perceptual saliency is low. Our technical system instance implementing the proposed architecture integrates several state-of-the-art methods in a coherent system and concentrates on unexpected motion as a first technical account of ventral attention. In our experiments, we demonstrate that the ventral attention enables our system to detect and reorient to important situations in real-world traffic environments that are relevant for the behavior of driving.

The paper is devoted to the problem of formalization of software-hardware solutions in designing real-time computer vision systems. The main attention is paid to the methods of implementation of low-level operations that find features (simple elements) in the image input to the system. Algorithmic types of detectors of simple elements in images are analyzed from the point of view of hardware organization in computer vision systems. In this connection, the necessary performance and memory resources are estimated. The capabilities of parallel and pipeline execution of detector algorithms are investigated. A method of using a field programmable gate array and a digital signal processor in solving the problem of image processing in real-time computer vision systems is considered in detail.

Programming a Pipelined Image Processor

Development of real-time visual monitoring system for vibration effects on fresh concrete

Implementation of a real-time image visualization system on a reconfigurable chip (FPGA) is proposed. The system utilizes an innovative stereoscopic image capture, processing and visualization technique. Implementation is done as a two stage process. In the first stage, the stereo pair is captured using two image sensors. The captured images are then synchronized and sent to the second stage for fusion. A controller module is developed, designed, and placed on the FPGA for this purpose. The second stage is used for reconstruction and visualization of the 3D image. An innovative technique employing dual-processor architecture on the same single FPGA is developed for this purpose. The whole system is placed on a single PCB resulting in a fast processing time and the ability to view 3D video in real-time. The system is simulated, implemented, and tested on real images. Results show that this system is a low cost solution for efficient 3D video visualization using a single chip.

Visualization is very useful for the study of the heart, but it is still a challenging work to display the detailed heart because of the complex structure and expensive computation. Very few systems have been developed to satisfy this work specially. In this paper, we designed and implemented a GPU-based and real-time cardiac visualization system (GRCVS). The illumination model and the context-preserving model are integrated into the system, so that it can generate better images and preserve the important boundary information at the same time. The rendering process is programmed with CUDA, which helps to view the final image in real time. The system also provides strong interactive ability: it supplies visual and concise interfaces to set various parameters which are used to adjust image effect and user can also use simple ways to observe the images quickly and conveniently. The system has been proved to be valuable for the study of the heart in biomedical field.

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we focus on Information-Centric Delay-Tolerant Network (ICDTN), which incorporates the communication paradigm of Information-Centric Networking (ICN) into Delay-Tolerant Networking (DTN). Conventional ICNs adopt a naming scheme that names the content with the content identifier. However, a past study proposed an alternative naming scheme that describes the name of content with the content descriptor. We believe that, in ICDTN, it is more suitable to utilize the approach using the content descriptor. In this paper, we therefore propose keyword-based ICDTN that resolves content requests and deliveries contents based on keywords, i.e., content descriptor, in the request and response messages.