Realization of 8x8 Memory Array using Optimized NVSRAM Cell

Static Random Access Memory (SRAM) is volatile and uses latching flip-flops to store each bit. To make SRAM work as non-volatile memory (NVM), memristor-based SRAM is a feasible choice mainly due to its high-speed operation and low power consumption. In this paper, the operational characteristics of 4T2M SRAM have been studied based on three different memristor models developed by Biolek et al. (2009), Joglekar and Wolf 2009, and Prodromakis et al. (2011), and comparative performance analysis has been made to assess its adaption to NVM. These three different models are compared in terms of delay, power consumption, and static noise margin. From the simulation, it has been observed that Biolek 4T2M SRAM produces better performance in write delay calculation scoring 0.873 ns when ‘0’ is written and 0.166 ns when ‘1’ is written. This model also provided a low power consumption value compared to other models. However, ternary plot analysis finds that Prodromakis is performing in average better in all positive traits. All the simulations are done in LTSpice and the transistor uses TSMC 180 nm CMOS technology.

The capability to protect against power fluctuations, which eventually prevents the corruption of the memory contents makes non-volatile static random access memory a very good choice for use in highly reliability applications. These random access memories are protected against data writing in addition to preserving the desired contents. Energy source and control circuitries are embedded into it for achieving the same. The control circuitry constantly monitors supply voltage level, inhibits data corruption, and switches on the energy source once it falls beyond a threshold level. In this paper, development of an abstract model for such a non-volatile static random access memory chip has been presented. Test sequences based on this model have been generated for this memory chip. These test sequences have been implemented in VLSI tester and exercised on the chips.

This article presents a new resistive random access memory (RRAM)-based average 7T1R nonvolatile static random access memory (nvSRAM). This multiple sharing (MS) 7T1R uses MS schemes in which some of the transistors play various roles. Therefore, the MS-7T1R can perform a decoupled read, enhance write capability, and improve the restore yield with a small area cost. Furthermore, the MS-7T1R can offer two alternative modes, i.e., a high speed and a stable mode. Compared with existing technologies, such as the previous 6T-based nvSRAMs, the results show that the proposed architecture provides a remarkable restore yield and ~154% improvement in the read static noise margin (at TT corner and stable mode). In addition, the read delay improves by ~23% (at TT corner and high-speed mode). The write "1" problem of the single bitline is effectively resolved with our proposed write strategy. The static write margin of "1" is improved by ~88.6% compared with the conventional 6T (β = 4) at a power of 1.2 V. In addition, dynamic power is effectively reduced by the use of the single bitline and sub-word-line driver technology.

Static Random-Access Memories (SRAMs) have flourished in the memory market relying on their speed, power consumption and compatibility with standard CMOS process technology. Conventional SRAMs are characterized by volatility, limiting their role in applications where non-volatility is essential. Non-Volatile SRAMs (NVSRAMs) represent an appealing solution, where Resistive RAM (RRAM) can act as a non-volatile element for SRAM. RRAM relies on the basic physical phenomenon of operation called resistive switching. This paper presents different NVSRAM structures, while exploring their principle of operation. Also, a comparison in terms of area, speed, power consumption and design complexity is presented for three NVSRAM memory cells implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.

Energy consumption is a major concern in nanoscale CMOS ICs; the power-Off operational mode and low-voltage circuits have been proposed to alleviate energy dissipation. Static random access memories (SRAMs) are widely used in today's chips; nonvolatile SRAMs (NVSRAMs) have been proposed to preserve data, while providing fast power- On/Off speeds. Nonvolatile operation is usually accomplished by the use of a resistive RAM circuit (hence referred to as RRAM); the utilization of a RRAM with an SRAMs not only enables chips to achieve low energy consumption for nonvolatile operation, but it also permits to restore data when a restore on power-up is performed (this operation is also commonly referred to as “Instant-on”). This paper presents a novel NVSRAM circuit for “Instant-on” operation and evaluates its performance at nanometric feature sizes. The proposed memory cell consists of a SRAM core (in this case, a 6T cell) and an oxide resistive RRAM circuit (1T1R), thus making a 7T1R scheme. The proposed cell offers better nonvolatile performance (in terms of operations such as “Store,” “Power-down,” and “Restore”) when compared with existing nonvolatile cells. The scenario of multiple-context configuration is also analyzed. Figures of merit such as energy, operational delay, and area are also substantially improved, making the proposed design a better scheme for “Instant-on” operation.

This paper investigates the static noise margin (SNM) of ultrathin-body (UTB) SOI SRAM 6T/8T cells operating in the subthreshold region using analytical solutions of Poisson's equation validated with TCAD simulations. An analytical framework to calculate the SNM for UTB SOI SRAMs operating in the subthreshold region is presented. Our results indicate that for improving both read SNM (RSNM) and write SNM (WSNM), the back-gating technique is more effective in the subthreshold region than in the superthreshold region. The 6T UTB SOI subthreshold SRAM cell with the back-gating technique by increasing the strength of the pull-up transistors and decreasing the strength of the pass-gate transistors shows comparable RSNM with the 10T bulk subthreshold SRAM and an improvement in RSNM variation. Due to better electrostatic integrity, the back-gating technique (pull-up transistors with positive back-gate bias, pull-down/pass-gate transistors with negative back-gate bias) mitigates the 6T UTB SOI SRAM RSNM variation significantly with some improvement in RSNM. Increasing cell beta-ratio shows a limited improvement on RSNM and has no benefit on the SNM variability for the subthreshold operation. The UTB SOI 8T SRAM cell exhibits RSNM 2times larger than the 6T SRAM cell in the subthreshold region. Both negative bit-line voltage (VBL) and boosted word-line voltage (VWL) are more effective than lower cell supply voltage to improve WSNM, and negative VBL shows a larger improvement in WSNM than boosted VWL.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

This work evaluates the performance of Neuromorphic architecture for accessing Static Random Access Memory (SRAM) in an asynchronous manner. Spike-Timing Dependent Plasticity (STDP) learning algorithm for updating the synaptic weights values in the SRAM module. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Memory array an important block in digital system. Bassically SRAM is used for increasing speed of the processor. Which is mostly connected between the DRAM and microprocessor. SRAM serves as cache memory which stores the information and losses its data without power. We may design the SRAM using 4T, 6T, 8T....for storing one bit. Sense amplifier is used to perform read and write operation. Instead of using sense amplifier we use the neural network concept. Synapse is connected between the SRAM and neuron. The minute gap across which nerve impulses pass from one neurone to the next, at the end of a nerve fiber. Each neurone has an enlarged portion the cell body, containing the nucleus; from the body extend several process through which impulses enter from their branches. A longer process, the nerve fiber, extends outwards and carries impulse away from the cell body. This is normally unbranched except at the nerve ending. This consumes less power than the normal memory circuit.

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an alternative material to silicon for high performance, high stability and low power Static Random Access Memory (SRAM) design in recent years. SRAM functions as cache memory in computers and many portable devices. Therefore, CNFET based SRAM cell design is desired for low standby power cache memory. In CNFET based six transistor SRAM cell, access transistors contribute significantly to the leakage power during standby mode. This paper proposes a technique to reduce the standby power of SRAM by scaling the channel length of access transistor. An optimum channel length is selected using HSPICE simulation to ensure best performance in terms of stability, standby power and write time. The proposed design results in 37.2% and 40.6% improvements in standby power and static noise margin (SNM) respectively compared to the conventional CNFET SRAM cell with minimal write time trade off.

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke has been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All of the chips that failed during the test recovered after enough venting.Hard disks were tested in severe environments but did not fail during the 2 h of monitoring.While the results of the tests documented in this report confirm that digital circuits can indeed be vulnerable to smoke, there is currently no practical, repeatable testing methodology, so it is not feasible to assess smoke susceptibility as part of environmental qualification. As a result, the most reasonable approach to minimizing smoke susceptibility is to employ design, implementation, and procedural practices that can reduce the possibility of smoke exposure and enhance smoke tolerance. Traditional approaches to mitigate its effects in digital safety instrumentation and control, such as redundancy, separation, defense in depth, as well as adherence to standards (e.g., the Institute of Electrical and Electronics Engineers’ IEEE 384) and the Code of Federal Regulations Appendix R of 10 CFR 50, should continue to be applied.

In this paper, the static noise margin (SNM) of FinFET static random access memory (SRAM) cells operating in the subthreshold region was investigated using an analytical solution of 3-D Poisson's equation. An analytical SNM model for subthreshold FinFET SRAM was demonstrated and validated by 3-D technology computer-aided design (TCAD) mixed-mode simulations. When compared with bulk SRAM, the standard 6T FinFET cell showed larger nominal READ SNM (RSNM), better variability immunity, and lesser temperature sensitivity of cell stability. Furthermore, examination of the stabilities of several novel independently controlled gate FinFET SRAM cells by using the proposed SNM model showed significant nominal RSNM improvements in these novel cells. However, the write ability is found to be degraded, which thus becomes an important concern for certain configurations in the subthreshold region. The result obtained indicates that the READ/WRITE word line voltage control technique is more effective than transistor sizing in improving the stability and write ability of the FinFET subthreshold SRAM. Furthermore, the impacts of process-induced variations on cell stability were also assessed. When compared with RSNM, it was found that WRITE SNM is more susceptible to process variations. While 6T is not a viable candidate for subthreshold SRAM, and 8T/10T cells must be used in bulk CMOS, the present analysis established the potential of 6T FinFET cells for subthreshold SRAM applications.

A nonvolatile SRAM has been designed and fabricated by integrating with ferroelectric HfO2 capacitors, and its store/recall operation before/after power-off have been experimentally demonstrated. Excellent ferroelectricity and memory characteristics have been obtained in sub-10nm-thick ferroelectric HfO2 capacitor. The NVSRAM with ferroelectric HfO2 capacitor can be a candidate for cost-effective, normally-off and ultralow power embedded memory solution for IoT power management. Introduction IoT edge devices have been playing key roles as sensor node device. The number of IoT edge devices is predicted to be trillions or even more, and then obviously the device must operate at ultralow power in the order of 1mW or less [1]. IoT edge device operates in an intermittent mode where the switching times of a transistor per second is very small in average. Then the power consumption is dominated by standby leakage current especially in high capacity memory such as SRAM. Therefore it is very important to suppress leakage current of a memory cell. One possible approach is to turn off power supply for memory cells. To do so, state information must be stored and recalled, before and after power-off, so that latency and power overhead are mitigated. This is so called normally-off computing and low power nonvolatile memory needs to be integrated to SRAM, which turns out to be nonvolatile SRAM (NVSRAM) [2-4]. There are several architectures for NVSRAM. Ferroelectric NVSRAM has an advantage of low voltage and low power operation [4]. However, conventional ferroelectric material has several issues in CMOS compatibility and scaling. Recently, ferroelectricity has been discovered in HfO2 thin film which is already used in CMOS process as a high-k dielectric [5-7]. Ferroelectric HfO2 opens new paths for ferroelectric-based low power devices including NVSRAM. In this paper, NVSRAM is designed and fabricated by integrating ferroelectric HfO2 in our university lab. We focus on functional device implementation as a proof-of-concept for normally-off computing and IoT power management. Device Operation and Design Consideration In this work, among several ferroelectric NVSRAM architectures [4,8-11], we chose 6T-2C NVSRAM architectures (Fig.1) [4] because of its simple structure, operation principle, and above all its simple process integration with ferroelectric HfO2 capacitor. NVSRAM cell is made of 6T SRAM cell and two ferroelectric capacitors at the SRAM nodes. Bottom electrodes of ferroelectric capacitors are connected to plate line (PL). NVSRAM operates just as normal SRAM with PL is VDD/2. It only needs to flip ferroelectric polarization during store operation before power-off, which mitigates reliability requirement of ferroelectric capacitors. One of the most critical operations is recall. The nodes have opposite polarizations and thus different capacitances. The recall operation makes use of this capacitance imbalance to regenerate node voltages. Capacitor size and voltage ramp rate need to be carefully chosen. We confirmed recall operation in our NVSRAM design by SPICE simulation which was calibrated by our MOSFET and MIM capacitor. Experiments and Discussions NVSRAM was fabricated by following process flow. First SRAM was fabricated by conventional SOI CMOS process. After contact formation, bottom TiN/Ti electrode was deposited by sputtering. Then HfO2 doped with Zr was deposited by ALD system, followed by top TiN electrode deposition by sputtering. MIMS capacitor was formed by simple subtractive etching process. Lastly, RTA was performed to crystalize the HfO2 film. Fig. 2 shows the cross sectional TEM image of the ferroelectric HfO2 capacitor, where we confirmed uniformly crystallized 9nm-thick HfO2 thin film. PV characteristics of the MIM capacitor integrated on SRAM cell does not show any degradation as shown in Fig. 3. We also confirmed sufficient capacitance difference for each polarization state. From retention measurement, more than 1 year retention is estimated. Measured endurance cycle was 1x108 which is close to requirement for IoT power management, 1x109. NVSRAM cell shows no difference in static SRAM butterfly curve from reference SRAM cell on the same chip. Fig. 4 shows the measured waveform of the entire NVSRAM operation. First, data was written in normal SRAM mode, and then store operation was performed before power-off. After arbitrary sleep time, recall operation was performed and the written data was verified. We confirmed correct store and recall operation in NVSRAM and demonstrated nonvolatile functionality with ferroelectric HfO2 capacitors. Summary We experimentally demonstrated the nonvolatile functionality of the NVSRAM integrated with ferroelectric HfO2 capacitor fabricated in the university lab. NVSRAM will enable normally-off computing for IoT power management at low cost. In this work, we focused on demonstrating essential store/recall operations. Design optimization for high density and high speed operation using relevant CMOS technology will be our future work. Figure 1

In this paper, statistical variability and different levels of BTI degradation are introduced into a compact model by statistical parameter extraction. Static Random Access Memory (SRAM) is used to test the compact model and to investigate the effects of MOSFET statistical variability and degradation at circuit level. Statistical distributions of Static Noise Margin (SNM) under different scenarios representing various degradation levels as well as mismatch levels between ‘on’ and the rest of the SRAM cell transistors are compared to investigate their impacts on SRAM stability. A surface response model of the dependence of the mean and standard deviation of SNM on circuit ageing and transient stress is also developed to quickly evaluate SRAM stability at arbitrary degradation levels.