Programmable synaptic memory with spiking neural network in VLSI

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

As CMOS scaling extends into the Nano scale tech-node, designers need to not only pay attention to the device behavior impact by traditional geometric parameters, such as channel length and width; but also need to be aware on layout implementation details of the device and its surrounding neighborhood. Static Random Access Memories (SRAM) 6T cell is a basic circuit constitute by six single device, including two PMOS and four NMOS. Large SRAM arrays are widely used as cache memory in electric industries and can be applied to monitor process quality and stability in manufacture process. The device performance of single device in SRAM 6T cell determined whether a SRAM cell can function, and seriously influenced the read/write margin of it. As the single device in SRAM 6T cell up against complicated layout surroundings, their performance is largely independent of the neighborhood environment. In this paper, we will focus on three types of local layout effect to SRAM single device, including NW size effect, metal boundary effect and gate extension AA size effect. The change mode of device in SRAM circuit is analyzed and mechanisms is investigated to explain them.

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

Low power feature associated with Static Random Access Memory (SRAM) is evaluated. By using gating transistor power saving technique (GTSPT), the average power of SRAM can be reduced. Using GTSPT scheme the average precharge current and the supply current is reduced which is the main cause of the power dissipation in the SRAM. While reading the data, the bitlines are always precharged. By reducing the precharge voltage, the power cane be saved. By using the sense amplifier, the data can be amplified for read operation. By adding the redundant rows and redundant columns the SRAM is made fault tolerant.

SRAM is the key element used in digital circuits. It is also used as a cache memory in computers, automatic modern equipment like mobile phones, modern appliances, digital calculators, digital cameras, so that the requirements of high-speed advanced memory or embedded memory lead to the development of low-voltage SRAMs. The paper has introduced the design and simulation of the distinctive source-based sense amplifier which is a peripheral circuit for static random access memory (SRAM) that has to amplify the data which is present on the bit lines during the read operation. Simulation of the proposed design has been implemented using 20 nm FinFET technology on the Cadence Virtuoso Tool with a supply voltage of +0.4 V. The main advantages from the proposed design circuit are less power consumption and display of minimum sense delay in sensing the data from SRAM when compared to the existing design circuit. A comparison is drawn between the proposed circuit and the existing design circuit.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

A high-speed sense amplifier capable of static random access memory (SRAM) applications has been developed in this work. The proposed sense amplifier can work at 1GHz with voltage as low as 1.8 V. Restated, the proposed sense amplifier can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Simulated results show that the proposed sense amplifier has 50/spl sim/87.5 % speed improvement compared to the conventional sense amplifiers.

The Static Random-Access Memory (SRAM) is the fundamental block in the larger memories. The SRAM memories are widely used because of its lower power consumption and delay. The SRAM memories are used in Cache memories. So, the delay of the circuit should be very less. The Non-Volatile memories are getting greater attention due to its Non-Volatile property. The circuits should have larger immunity to noise voltages. So, the Static Noise Margin (SNM) of the circuits should be very high. In this paper, the VTEAM model based Memristor has been designed. The 7T1M Non-Volatile SRAM (NVSRAM) has been proposed for the higher SNM value. The proposed 7T1M NVSRAM cell and existing 7T2M NVSRAM cell has SNM values of 0.518V and 0.04V respectively. The Average Restore time of 7T1M NVSRAM is decreased by 66% when compared to the 7T2M NVSRAM Cell. The different peripheral components like Write driver circuit, Precharge circuit, Row and Column Decoder and Sense Amplifier have been designed. The 8x8 Non Volatile Memory array has been designed using the proposed 7T1M NVSRAM cell and peripheral circuits. All the design is done using the Cadence Virtuoso tool at 45 nm technology with an operating voltage of 1.2 V.

In digital systems, Static Random Access Memories (SRAMs) play an important role since they are available in almost every digital devices and are able to realize Physically Unclonable Functions (PUFs), which can enable security primitives over a wide range of devices without needing additional hardware resources. Indeed, each SRAM presents an unpredictable and unique pattern, established when they are powered-up, which can be useful as key generator and for authentication mechanisms. Before exploiting SRAMs as PUFs, they have to be qualified in terms of stability since the pattern behavior of SRAMs might be heavily influenced by a wide variety of working conditions, such as temperature and applied voltage. In this paper we present the result of an experimental campaign, conducted over real 90nm SRAMs, which aim is to deeply investigate the power-up pattern behavior under different power supply strategies through the PUF quality analysis. In particular we show the reliability, uniqueness and uniformity for SRAMs embedded in STM32F3 and STM32F4 microcontrollers for more than 50 devices.

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Serious reliability concerns of Static Random Access Memories (SRAMs) in nanometer technologies are the increased process variations as well as the various aging mechanisms. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena are the main factors related to the aging reliability reduction. This degradation affects speed, operating voltages, memory cell noise margins and sense amplifier input offset voltage. Thus, it is imperative to develop design techniques for aging tolerance that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation. In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers and memory cells is presented.

This paper combines several low-leakage and low-cost techniques to design multi-port static random access memory (SRAM) for register file in a vertex shader processor for OpenGL ES 2.0 graphics applications. First, precharge control is employed to eliminate unnecessary precharge operations. Then, dynamic forward body-bias control for leakage reduction is proposed to adjust the threshold voltage of transistors depending on whether memory cell is accessed or idle. Different power-gating methods are presented for SRAM cells and for sense amplifiers. The thin-cell-like lithography-friendly layout style is adopted for the multi-port SRAM cell to achieve more compact and flexible layout with easy addition of read ports. The cross-coupled inverters in the SRAM cell have asymmetric design to reduce area and also increase the writability. A 32×128-bit register file supporting 5-read and 1-write operations is implemented and verified, which has smaller area and lower leakage compared with that from ARM register file generator.

Carbon Nanotube Field Effect Transistor (CNFET) has emerged as an alternative material to silicon for high performance, high stability and low power Static Random Access Memory (SRAM) design in recent years. SRAM functions as cache memory in computers and many portable devices. Therefore, CNFET based SRAM cell design is desired for low standby power cache memory. In CNFET based six transistor SRAM cell, access transistors contribute significantly to the leakage power during standby mode. This paper proposes a technique to reduce the standby power of SRAM by scaling the channel length of access transistor. An optimum channel length is selected using HSPICE simulation to ensure best performance in terms of stability, standby power and write time. The proposed design results in 37.2% and 40.6% improvements in standby power and static noise margin (SNM) respectively compared to the conventional CNFET SRAM cell with minimal write time trade off.

Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for an SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology scaling, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 /spl mu/m and below.

Smoke can cause interruptions and upsets in active electronics. Because nuclear power plants are replacing analog with digital instrumentation and control systems, qualification guidelines for new systems are being reviewed for severe environments such as smoke and electromagnetic interference. Active digital systems, individual components, and active circuits have been exposed to smoke in a program sponsored by the U.S. Nuclear Regulatory Commission. The circuits and systems were all monitored during the smoke exposure, indicating any immediate effects of the smoke. The results of previous smoke exposure studies have been reported in various publications. The major immediate effect of smoke has been to increase leakage currents and to cause momentary upsets and failures in digital systems. This paper presents new results from conformal coatings, memory chips, and hard drive tests.The best conformal coatings were found to be polyurethane, parylene, and acrylic (when applied by dipping). Conformal coatings can reduce smoke-induced leakage currents and protect against metal loss through corrosion. However conformal coatings are typically flammable, so they do increase material flammability. Some of the low-voltage biased memory chips failed during a combination of high smoke and high humidity. Typically, smoke along with heat and humidity is expected during fire, rather than smoke alone. Thus, due to high sensitivity of digital circuits to heat and humidity, it is hypothesized that the impact of smoke may be secondary.Low-voltage (3.3-V) static random-access memory (SRAMs) were found to be the most vulnerable to smoke. Higher bias voltages decrease the likelihood of failure. Erasable programmable read-only memory (EPROMs) and nonvolatile SRAMs were very smoke tolerant. Failures of the SRAMs occurred when two conditions were present: high density of smoke and high humidity. As the high humidity was present for only part of the test, the failures were intermittent. All of the chips that failed during the test recovered after enough venting.Hard disks were tested in severe environments but did not fail during the 2 h of monitoring.While the results of the tests documented in this report confirm that digital circuits can indeed be vulnerable to smoke, there is currently no practical, repeatable testing methodology, so it is not feasible to assess smoke susceptibility as part of environmental qualification. As a result, the most reasonable approach to minimizing smoke susceptibility is to employ design, implementation, and procedural practices that can reduce the possibility of smoke exposure and enhance smoke tolerance. Traditional approaches to mitigate its effects in digital safety instrumentation and control, such as redundancy, separation, defense in depth, as well as adherence to standards (e.g., the Institute of Electrical and Electronics Engineers’ IEEE 384) and the Code of Federal Regulations Appendix R of 10 CFR 50, should continue to be applied.