High-speed sense amplifier for SRAM applications

Thin-film transistor (TFT) not only is the backbone of display technology, but also brings in fancy applications in the area of flexible electronics. TFT-based flexible circuit design however faces various challenges, such as unipolar devices and severe nonuniformity. In this paper, a sense amplifier based on dual-gate indium-gallium-zinc oxide (IGZO) TFTs is proposed for TFT-based static random access memory (SRAM) circuits. The pull-up transistors in the proposed sense amplifier are implemented with dual-gate TFTs while the pull-down transistors are implemented with conventional bottom-gate TFTs. By tuning the top gate of the pull-up transistors to achieve a negative threshold voltage as well as employing a specialized strength- adaptive pull-up structure, the proposed sense amplifier aims to reduce the offset voltage, sensing delay, and sensing power consumption simultaneously. Compared to the state-of-the-art IGZO-based sense amplifier, the proposed sense amplifier achieves up to 66.1% lower offset voltage, 68.9% shorter sensing delay, 72% dynamic power savings, and 66.3% leakage power savings.

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 /spl mu/m CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.

This work evaluates the performance of Neuromorphic architecture for accessing Static Random Access Memory (SRAM) in an asynchronous manner. Spike-Timing Dependent Plasticity (STDP) learning algorithm for updating the synaptic weights values in the SRAM module. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Memory array an important block in digital system. Bassically SRAM is used for increasing speed of the processor. Which is mostly connected between the DRAM and microprocessor. SRAM serves as cache memory which stores the information and losses its data without power. We may design the SRAM using 4T, 6T, 8T....for storing one bit. Sense amplifier is used to perform read and write operation. Instead of using sense amplifier we use the neural network concept. Synapse is connected between the SRAM and neuron. The minute gap across which nerve impulses pass from one neurone to the next, at the end of a nerve fiber. Each neurone has an enlarged portion the cell body, containing the nucleus; from the body extend several process through which impulses enter from their branches. A longer process, the nerve fiber, extends outwards and carries impulse away from the cell body. This is normally unbranched except at the nerve ending. This consumes less power than the normal memory circuit.

In this work, the authors propose a 4F2 (F is the length of half pitch) memory cell with a vertical PNPN structure (silicon device with 4 layers doped with p-type, n-type, p-type and n-type dopants, respectively) to increase static random access memory (SRAM) integration density compared to the traditional 6T SRAM cell with an area of 90 ∼ 150F2. Thanks to the simple two-terminal configuration, the cross-point structure with proposed cell can be used in memory design, to achieve the highest density in planar complementary metal oxide semiconductor (CMOS) technology and to be implemented potentially in future three-dimensional integration. Experimental results demonstrate that the fabrication of proposed memory cell is compatible with CMOS process, little impact by process variation and reliability issues. Calibrated simulations display that the proposed cell can be programmed at nanosecond level speed with acceptable power consumption in most memory applications.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Low power feature associated with Static Random Access Memory (SRAM) is evaluated. By using gating transistor power saving technique (GTSPT), the average power of SRAM can be reduced. Using GTSPT scheme the average precharge current and the supply current is reduced which is the main cause of the power dissipation in the SRAM. While reading the data, the bitlines are always precharged. By reducing the precharge voltage, the power cane be saved. By using the sense amplifier, the data can be amplified for read operation. By adding the redundant rows and redundant columns the SRAM is made fault tolerant.

Serious reliability concerns of Static Random Access Memories (SRAMs) in nanometer technologies are the increased process variations as well as the various aging mechanisms. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena are the main factors related to the aging reliability reduction. This degradation affects speed, operating voltages, memory cell noise margins and sense amplifier input offset voltage. Thus, it is imperative to develop design techniques for aging tolerance that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation. In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers and memory cells is presented.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

We present a comparative analysis of a fabricated 65nm CMOS static random access memory (SRAM) chip and commercial SRAM chips in terms of security vulnerability. The security vulnerability is defined as the leakage of information due to the data imprinting effect of the SRAM. There are three main features in this evaluation. First, a complete security vulnerability evaluation flow is proposed to stress the SRAM chips for accelerating the negative-biased temperature-instability (NBTI) degradation, i.e. data imprinting effect, and hence to reveal the stored data of image. Second, the evaluation quantifies the percentage of revealed data, i.e. leakage of information for the comparison of tested SRAMs. Third, the image is reconstructed from the revealed data to illustrate the security vulnerabilities of tested SRAMs. We perform the security vulnerability evaluation on the 65nm CMOS SRAM chip and 4 commercial SRAM chips, namely Alliance, Lyontek, Cypress and AMIC under stressing of high voltage and high temperature. From the experimental results, the stored data is significantly revealed in the deep-submicron (≤90nm) CMOS SRAM chips, i.e. fabricated 65nm CMOS (16.1%), Alliance (16.2%) and Lyontek (21%). After reconstructing the images, they can be identified in the 65nm CMOS, Alliance, Lyontek SRAMs, but remain as random states in the Cypress and AMIC SRAMs.

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronics device, draws wide attention for its low current drive, non-volatility, small size, infinite erasure, and low standby power. It is widely used in magnetic random-access memory (MRAM) or embedded in CMOS logical circuits. In this paper, a novel high speed, low resource and non-volatile MTJ-CMOS hybrid logical circuit structure is proposed, which consists of Multi-Voltage controlled Multi-Write (MVMW) write circuit and High-Speed Sense Amplifier (HSSA) circuit. The MVMW write circuit enhances the write speed by shortening the critical path while achieving two independent write controls of the MTJs. Also, a voltage comparator sense amplifier is employed to increase the read speed (about 110ps). By using a dynamic compact MTJ model and 55 nm CMOS design kit, we designed a circuit architecture which can be used to form all kinds of logical computations. An AND/NAND logical is used to demonstrate functionality of the architecture and compared it with a traditional MTJ-CMOS hybrid circuit. The proposed non-volatile MTJ-CMOS hybrid circuit uses only 62.5% of resources, achieving a 4.37X write speed and a 2.64X read speed. The overall average speed increases 3.12 times with similar power consumption. Moreover, it is compatible for asynchronous circuits design.

Simple models for the delay, power, and area of a static random access memory (SRAM) are used to determine the optimal organizations for an SRAM and study the scaling of their speed and power with size and technology. The delay is found to increase by about one gate delay for every doubling of the RAM size up to 1 Mb, beyond which the interconnect delay becomes an increasingly significant fraction of the total delay. With technology scaling, the nonscaling of threshold mismatches in the sense amplifiers is found to significantly impact the total delay in generations of 0.1 /spl mu/m and below.