Speed and power scaling of SRAM's

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

This work evaluates the performance of Neuromorphic architecture for accessing Static Random Access Memory (SRAM) in an asynchronous manner. Spike-Timing Dependent Plasticity (STDP) learning algorithm for updating the synaptic weights values in the SRAM module. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Memory array an important block in digital system. Bassically SRAM is used for increasing speed of the processor. Which is mostly connected between the DRAM and microprocessor. SRAM serves as cache memory which stores the information and losses its data without power. We may design the SRAM using 4T, 6T, 8T....for storing one bit. Sense amplifier is used to perform read and write operation. Instead of using sense amplifier we use the neural network concept. Synapse is connected between the SRAM and neuron. The minute gap across which nerve impulses pass from one neurone to the next, at the end of a nerve fiber. Each neurone has an enlarged portion the cell body, containing the nucleus; from the body extend several process through which impulses enter from their branches. A longer process, the nerve fiber, extends outwards and carries impulse away from the cell body. This is normally unbranched except at the nerve ending. This consumes less power than the normal memory circuit.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

We present a comparative analysis of a fabricated 65nm CMOS static random access memory (SRAM) chip and commercial SRAM chips in terms of security vulnerability. The security vulnerability is defined as the leakage of information due to the data imprinting effect of the SRAM. There are three main features in this evaluation. First, a complete security vulnerability evaluation flow is proposed to stress the SRAM chips for accelerating the negative-biased temperature-instability (NBTI) degradation, i.e. data imprinting effect, and hence to reveal the stored data of image. Second, the evaluation quantifies the percentage of revealed data, i.e. leakage of information for the comparison of tested SRAMs. Third, the image is reconstructed from the revealed data to illustrate the security vulnerabilities of tested SRAMs. We perform the security vulnerability evaluation on the 65nm CMOS SRAM chip and 4 commercial SRAM chips, namely Alliance, Lyontek, Cypress and AMIC under stressing of high voltage and high temperature. From the experimental results, the stored data is significantly revealed in the deep-submicron (≤90nm) CMOS SRAM chips, i.e. fabricated 65nm CMOS (16.1%), Alliance (16.2%) and Lyontek (21%). After reconstructing the images, they can be identified in the 65nm CMOS, Alliance, Lyontek SRAMs, but remain as random states in the Cypress and AMIC SRAMs.

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

Low power feature associated with Static Random Access Memory (SRAM) is evaluated. By using gating transistor power saving technique (GTSPT), the average power of SRAM can be reduced. Using GTSPT scheme the average precharge current and the supply current is reduced which is the main cause of the power dissipation in the SRAM. While reading the data, the bitlines are always precharged. By reducing the precharge voltage, the power cane be saved. By using the sense amplifier, the data can be amplified for read operation. By adding the redundant rows and redundant columns the SRAM is made fault tolerant.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

A high-speed sense amplifier capable of static random access memory (SRAM) applications has been developed in this work. The proposed sense amplifier can work at 1GHz with voltage as low as 1.8 V. Restated, the proposed sense amplifier can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Simulated results show that the proposed sense amplifier has 50/spl sim/87.5 % speed improvement compared to the conventional sense amplifiers.

Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena degrading nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI). This paper proposes a new approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. The sensor is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM contents after testing. To prevent OCAS from aging by one side and from dissipating static power by the other side, OCAS circuitry is powered-off during idle periods. SPICE simulations in a 65nm CMOS technology demonstrate the high sensor sensitivity to detect early aging states and so, guarantying high memory reliability. Furthermore, area overhead due to sensor insertion is almost negligible.

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presents the design and simulation of a 16-bit $\times 32$ -bit SRAM with a new structure in QCA. Since QCA is a pipeline, this SRAM has a high operating speed. The 16-bit $\times 32$ -bit SRAM has a new structure with a 32-bit width designed and implemented in QCA. It has the ability of a conventional logic SRAM that can provide read/write operations frequently with minimum delay. The 16-bit $\times 32$ -bit SRAM is generalized and an $n\times 16$ -bit $\times 32$ -bit SRAM is implemented in QCA. Novel 16-bit decoders and multiplexers (MUXs) in QCA are presented that have been designed with a minimum number of majority gates and cells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA using a signal distribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAM cell was compared with the SRAM cell based on CMOS. Results show that the proposed SRAM is more efficient in terms of area, complexity, clock frequency, latency, throughput, and power consumption.

In this chapter, modelling of Negative Bias Temperature Instability (NBTI), how it is incorporated with Static Random Access Memory (SRAM) and its impact on different SRAM cache configurations is presented. Investigations of how NBTI affects different power saving cache strategies employing the standard symmetric and asymmetric 6-transistor (6T) SRAM, and the isolated read-port 6T SRAM bitcells, are presented. It is observed that more than 38–66% of the recovery in stability parameters (SNM and WNM) under different power saving cache strategies have been achieved for different SRAM bitcells based cache configurations. It is also found that the low V TH transistors age faster than the high V TH transistors due to NBTI. Hence, NBTI effect is more pronounced in future technologies due to reduction in V TH with technology scaling. Also NBTI effect is more significant at higher temperature.

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

As CMOS scaling extends into the Nano scale tech-node, designers need to not only pay attention to the device behavior impact by traditional geometric parameters, such as channel length and width; but also need to be aware on layout implementation details of the device and its surrounding neighborhood. Static Random Access Memories (SRAM) 6T cell is a basic circuit constitute by six single device, including two PMOS and four NMOS. Large SRAM arrays are widely used as cache memory in electric industries and can be applied to monitor process quality and stability in manufacture process. The device performance of single device in SRAM 6T cell determined whether a SRAM cell can function, and seriously influenced the read/write margin of it. As the single device in SRAM 6T cell up against complicated layout surroundings, their performance is largely independent of the neighborhood environment. In this paper, we will focus on three types of local layout effect to SRAM single device, including NW size effect, metal boundary effect and gate extension AA size effect. The change mode of device in SRAM circuit is analyzed and mechanisms is investigated to explain them.

Serious reliability concerns of Static Random Access Memories (SRAMs) in nanometer technologies are the increased process variations as well as the various aging mechanisms. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena are the main factors related to the aging reliability reduction. This degradation affects speed, operating voltages, memory cell noise margins and sense amplifier input offset voltage. Thus, it is imperative to develop design techniques for aging tolerance that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation. In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers and memory cells is presented.

Wide-spread availability of high-speed INTERNET and rapid increase of smart-phone users have significantly increased online video surfing. Video decoders like H.264/H.265/MPEG consume a significant amount of power in Static Random Access Memory (SRAM) buffers. In this study, the authors propose a 1 kb (32 × 32) heterogeneous 8T SRAM architectures with (2-lower order bits) and without truncation for H.264 video decoder. They have used heterogeneous sized SRAM design and bit-truncation techniques are used simultaneously to obtain low power memory design for the H.264 video decoder. They show that the proposed approximate memory used for H.264 video decoder provide high video quality even at low power and low area budget of 0.3 µW/pixel and 5.2 µm 2 /pixel, respectively, at 0.5 V and 20 MHz in UMC 28 nm CMOS technology. The proposed memory architecture is compared with existing approximate memories such as heterogeneous 6T, hybrid 8T/6T, all-identical 6T, and all-identical 8T SRAM memory. The results show that proposed memory architectures perform cumulatively better than existing techniques in terms of dynamic power, leakage power, and area.