Aging Prediction and Tolerance for the SRAM Memory Cell and Sense Amplifier

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

This work evaluates the performance of Neuromorphic architecture for accessing Static Random Access Memory (SRAM) in an asynchronous manner. Spike-Timing Dependent Plasticity (STDP) learning algorithm for updating the synaptic weights values in the SRAM module. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Memory array an important block in digital system. Bassically SRAM is used for increasing speed of the processor. Which is mostly connected between the DRAM and microprocessor. SRAM serves as cache memory which stores the information and losses its data without power. We may design the SRAM using 4T, 6T, 8T....for storing one bit. Sense amplifier is used to perform read and write operation. Instead of using sense amplifier we use the neural network concept. Synapse is connected between the SRAM and neuron. The minute gap across which nerve impulses pass from one neurone to the next, at the end of a nerve fiber. Each neurone has an enlarged portion the cell body, containing the nucleus; from the body extend several process through which impulses enter from their branches. A longer process, the nerve fiber, extends outwards and carries impulse away from the cell body. This is normally unbranched except at the nerve ending. This consumes less power than the normal memory circuit.

This paper combines several low-leakage and low-cost techniques to design multi-port static random access memory (SRAM) for register file in a vertex shader processor for OpenGL ES 2.0 graphics applications. First, precharge control is employed to eliminate unnecessary precharge operations. Then, dynamic forward body-bias control for leakage reduction is proposed to adjust the threshold voltage of transistors depending on whether memory cell is accessed or idle. Different power-gating methods are presented for SRAM cells and for sense amplifiers. The thin-cell-like lithography-friendly layout style is adopted for the multi-port SRAM cell to achieve more compact and flexible layout with easy addition of read ports. The cross-coupled inverters in the SRAM cell have asymmetric design to reduce area and also increase the writability. A 32×128-bit register file supporting 5-read and 1-write operations is implemented and verified, which has smaller area and lower leakage compared with that from ARM register file generator.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

Dynamic supply current test method (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> test) in static random access memory (SRAM) cell arrays is addressed in order to unveil weak open defects. Simulations were carried out on a 64-bit SRAM circuit, where several parameters of the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> waveform were monitored. The SRAM circuit was designed in a 90 nm CMOS technology. Efficiency of I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDT</sub> test in unveiling open defects was evaluated and the achieved results were compared for four SRAM arrays with cells of different cell ratio (CR). Moreover, a solution for transformation of the dynamic current to voltage is presented. After the transformation of the current waveform to a voltage waveform, the parameters of the voltage waveform similar to those of the current waveform are easily monitored and evaluated.

A low power CMOS Static Random Access Memory (SRAM) based Field Programmable Gate Arrays (FPGA) architecture is being presented in this paper. The architecture presented here is based on CMOS logic and CMOS SRAMs that are used for on-chip dynamic reconfiguration. This architecture employs the fast and low-power SRAM blocks that are based on 10T SRAM cells. These blocks are employed in fast access of the configuration bits by using the shadow SRAM technique. The dynamic reconfiguration delay is being hidden behind the computation delay through the use of shadow SRAM cells. The combined effect of both the SRAM memory cells and the shadow SRAM scheme enables to support in reducing the delay and also to achieve reduced power consumption. Experimental results show reduced delay of about 8.035ns and power consumption of about 0.015W for the 10T SRAM memory cell with an overhead in area, relative to 4T and 6T SRAM cells. Also, the experimental results include the values of delay of about 8.979ns and power consumption of about 0.052W, achieved for the LB of FPGA architecture which employs CMOS SRAMs using the 10T SRAM memory cells in it.

Static random access memories (SRAM) are widely used in computer systems and many portable devices. In this paper, we propose an SRAM cell with dual threshold voltage transistors. Low threshold voltage transistors are mainly used in driving bit-lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Also, the unwanted oscillation of the output bitlines of memories caused by large currents in bitlines is reduced by adding two back-to-back quenchers. The proposed quenchers not only prevent oscillation, but also reduce the idle power consumption when the memory cells are not activated by wordline signals. Meanwhile, a large noise margin is provided such that the gain of the sense amplifier will not be reduced to avoid the oscillation. Hence, high-speed and low-power readout operations of the SRAMs are feasible.

-As the demand for low-power, high-performance memory systems grows, the design of efficient SRAM (Static Random Access Memory) cells becomes increasingly crucial. This paper explores the power consumption, performance, and stability of two SRAM cell designs: the conventional 6T and the Single Ended 6T SRAM. While the conventional 6T SRAM is prone to read disturb noise and high leakage power, it remains widely used due to its simplicity and compactness. To address these issues, the Single Ended 6T SRAM cell is introduced as an alternative, which reduces both power consumption and area while maintaining competitive performance. The study provides a detailed analysis of static and dynamic power consumption, read/write stability, and overall energy efficiency for both cell architectures. Simulation results show that the Single Ended 6T SRAM offers significant improvements in power reduction without compromising speed, making it a promising solution for future low-power, high-performance memory applications. Keywords— SRAM cell, Pre-Charge Circuits, Sense Amplifiers, and Single-Ended vs. Conventional 6T SRAM Cell.

Low power feature associated with Static Random Access Memory (SRAM) is evaluated. By using gating transistor power saving technique (GTSPT), the average power of SRAM can be reduced. Using GTSPT scheme the average precharge current and the supply current is reduced which is the main cause of the power dissipation in the SRAM. While reading the data, the bitlines are always precharged. By reducing the precharge voltage, the power cane be saved. By using the sense amplifier, the data can be amplified for read operation. By adding the redundant rows and redundant columns the SRAM is made fault tolerant.

A high-speed sense amplifier capable of static random access memory (SRAM) applications has been developed in this work. The proposed sense amplifier can work at 1GHz with voltage as low as 1.8 V. Restated, the proposed sense amplifier can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Simulated results show that the proposed sense amplifier has 50/spl sim/87.5 % speed improvement compared to the conventional sense amplifiers.

&lt;p&gt;Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.&lt;/p&gt;

In recent years, FinFET-based Static Random Access Memories (SRAMs) have become a viable solution to provide the storage of big data volume in Systems-on-Chip (SoCs) as well as to assure high performance deep-scaled devices. As consequence, FinFET-based SRAMs are an extremely viable solution to guarantee the high-performance requirements of deep-scaled devices. However, FinFET-based SRAMs can also be affected by resistive defects that may lead to dynamic faults, which are considered one of the most important causes of manufacturing test escape in deep-submicron technologies. Hence, this paper proposes to evaluate the impact of temperature on the dynamic faulty behaviour of 20 nm FinFET-based SRAM cells affected by weak resistive defects. In more details, the critical resistances and the number of consecutive operations necessary to sensitize faults at the logic level are investigated. Additionally, the concept of Dynamic Behaviour Window (DBW) is defined. Results showed that temperature plays a major part in the sensitization of dynamic faults. Thus, the occurrence of dynamic faults has been mapped combining temperature as well as defect size, and the DBW has been defined considering resistive defects. The proposed evaluation helps to understand the behaviour of dynamic faults in memory cells even better and therefore can be used to improve the test procedures for deep-scaled FinFET memory devices. The proposed analysis has been performed using HSPICE simulations adopting a 20 nm Predictive Technology Model (PTM) of multi-gate transistors based on bulk FinFET.

We present a comparative analysis of a fabricated 65nm CMOS static random access memory (SRAM) chip and commercial SRAM chips in terms of security vulnerability. The security vulnerability is defined as the leakage of information due to the data imprinting effect of the SRAM. There are three main features in this evaluation. First, a complete security vulnerability evaluation flow is proposed to stress the SRAM chips for accelerating the negative-biased temperature-instability (NBTI) degradation, i.e. data imprinting effect, and hence to reveal the stored data of image. Second, the evaluation quantifies the percentage of revealed data, i.e. leakage of information for the comparison of tested SRAMs. Third, the image is reconstructed from the revealed data to illustrate the security vulnerabilities of tested SRAMs. We perform the security vulnerability evaluation on the 65nm CMOS SRAM chip and 4 commercial SRAM chips, namely Alliance, Lyontek, Cypress and AMIC under stressing of high voltage and high temperature. From the experimental results, the stored data is significantly revealed in the deep-submicron (≤90nm) CMOS SRAM chips, i.e. fabricated 65nm CMOS (16.1%), Alliance (16.2%) and Lyontek (21%). After reconstructing the images, they can be identified in the 65nm CMOS, Alliance, Lyontek SRAMs, but remain as random states in the Cypress and AMIC SRAMs.

Application of quantum-dot cellular automata (QCA) technology as an alternative to CMOS technology on the nanoscale has a promising future; QCA is an interesting technology for building memory. The proposed design and simulation of a new memory cell structure based on QCA with a minimum delay, area, and complexity is presented to implement a static random access memory (SRAM). This paper presents the design and simulation of a 16-bit $\times 32$ -bit SRAM with a new structure in QCA. Since QCA is a pipeline, this SRAM has a high operating speed. The 16-bit $\times 32$ -bit SRAM has a new structure with a 32-bit width designed and implemented in QCA. It has the ability of a conventional logic SRAM that can provide read/write operations frequently with minimum delay. The 16-bit $\times 32$ -bit SRAM is generalized and an $n\times 16$ -bit $\times 32$ -bit SRAM is implemented in QCA. Novel 16-bit decoders and multiplexers (MUXs) in QCA are presented that have been designed with a minimum number of majority gates and cells. The new SRAM, decoders, and MUXs are designed, implemented, and simulated in QCA using a signal distribution network to avoid the coplanar problem of crossing wires. The QCA-based SRAM cell was compared with the SRAM cell based on CMOS. Results show that the proposed SRAM is more efficient in terms of area, complexity, clock frequency, latency, throughput, and power consumption.

Thin-film transistor (TFT) not only is the backbone of display technology, but also brings in fancy applications in the area of flexible electronics. TFT-based flexible circuit design however faces various challenges, such as unipolar devices and severe nonuniformity. In this paper, a sense amplifier based on dual-gate indium-gallium-zinc oxide (IGZO) TFTs is proposed for TFT-based static random access memory (SRAM) circuits. The pull-up transistors in the proposed sense amplifier are implemented with dual-gate TFTs while the pull-down transistors are implemented with conventional bottom-gate TFTs. By tuning the top gate of the pull-up transistors to achieve a negative threshold voltage as well as employing a specialized strength- adaptive pull-up structure, the proposed sense amplifier aims to reduce the offset voltage, sensing delay, and sensing power consumption simultaneously. Compared to the state-of-the-art IGZO-based sense amplifier, the proposed sense amplifier achieves up to 66.1% lower offset voltage, 68.9% shorter sensing delay, 72% dynamic power savings, and 66.3% leakage power savings.