A Pull-Up Adaptive Sense Amplifier Based on Dual-Gate IGZO TFTs

A high-speed sense amplifier capable of static random access memory (SRAM) applications has been developed in this work. The proposed sense amplifier can work at 1GHz with voltage as low as 1.8 V. Restated, the proposed sense amplifier can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Simulated results show that the proposed sense amplifier has 50/spl sim/87.5 % speed improvement compared to the conventional sense amplifiers.

A dual-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistor (TFT) was studied to obtain a pH sensitivity of $\sim 160$ mV/pH, which is above Nernst limit (59 mV/pH) with a low value of operating voltage (−5 to 5 V). The utilization of the active layer itself as the sensitive surface constitutes the dual-gate TFT structure with the back-channel gated with the electrolyte. The TFT characteristics were optimized by annealing the IGZO film in varying temperatures in oxygen ambience. A double-layered a-IGZO was used to sandwich the source/drain electrodes to eliminate the issues related with the high contact resistance and critical passivation of source/drain electrodes to protect from the exposure of the electrolyte. The single-gate electrolyte-gated thin film transistor showed the pH sensitivity of 24 mV/pH, which was enhanced by 6.7-fold by its dual-gate operation. The operation of dual-gate TFT ion-sensitive field-effect transistors (ISFETs) with varying only bottom gate voltage eliminates the requirement of a reference electrode necessary in single-gate ISFETs. Such dual-gate ISFETs obviate the need of an additional high- $K$ dielectric needed for the dual-gate TFT ISFETs and could also be fabricated on flexible substrates. These structures with the high sensitivity of $\sim 160$ mV/pH and requiring low ( $\sim 2~\mu \text{L}$ ) analyte solution could be the potential candidates for utilization as chemical and bio-sensors.

Indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) have attracted much attention because of their high electron mobility values (> 10 cm2/Vs) and because they can be processed at low temperature to produce large-area displays with the potential of low production costs. The IGZO TFTs require smaller RC signal delay with shorter channel length for high-resolution display applications. Therefore, it’s necessary to use self-aligned top-gate (TG) oxide TFT structure with smaller channel length for high-resolution, high-speed, low-power, and narrow-bezel displays. The IGZO TFTs also need good electrical stability under positive/negative bias temperature stress (P/NBTS) with decent TFT properties for peripheral gate driver integrated large size organic light emitting diode (OLED) TVs. TG IGZO TFTs for display applications such as OLED TVs typically use longer channel length (> 4 µm) due to negative threshold voltage (Vth) shift and Vth non-uniformity issues with smaller channel length, which is mainly caused by hydrogen diffusion near source/drain regimes during device integration. We fabricated TG IGZO TFTs by using Applied Material’s CVD/PVD tools to achieve excellent electrical stability and Vth uniformity by balancing oxygen and hydrogen diffusion into oxide channel layer such as IGZO. Suppressing carrier densities at the interface between gate insulator (GI) and IGZO by increasing oxygen diffusion with IGZO pre-annealing in air and TFT post anneal in air, and by minimizing vacuum annealing impact during GI deposition makes the IGZO TFTs more resistive with more positive Vth shift. On the other hands, more hydrogen diffusion into IGZO from GI, ILD, and passivation layers during device integration or TFT post annealing makes the IGZO TFTs more conductive with more negative Vth shift and worse Vth uniformity, but it helps to improve electrical stability with smaller Vth shift under PBTS by passivating defects inside IGZO. Therefore, there is trade-off between Vth uniformity and electrical stability due to the dominance of the diffusion between oxygen and hydrogen. By balancing the diffusion of oxygen and hydrogen, the IGZO TFTs can minimize negative Vth shift even with shorter channel for high-resolution display applications and achieve good electrical stability for pixel and peripheral gate driver circuits integrated in display panel. We successfully demonstrated excellent electrical properties such as high mobility (µFE), low sub-threshold slope (SS), good threshold voltage (Vth) position, and low off-leakage current from TG IGZO TFTs. The positions of Vth can be optimized by controlling carrier densities at the interface between GI and IGZO during device integration even with different GI temperature and power (Fig. 1). Here, GI type A is deposited at a low temperature of 225 ºC with a high RF power of 2400 W. GI type B is deposited at a high temperature of 270 ºC with a high RF power of 2400 W. GI type C is deposited at a high temperature of 270 ºC with a low RF power of 1600 W. In order to investigate the channel length dependency of Vth, Vth values were extracted from transfer characteristics at VDS = +1 V with various TFTs by fixing channel width of 12 µm and varying the channel length from 10 µm down to 3 µm. The differences between maximum Vth and minimum Vth, Vth (Max–Min), from GI type A, B, and C are 0.35 V, 0.48 V, and 1.20 V, respectively. Total resistance in TFTs was extracted from the measured IDS values by varying VGS from 12 V to 20 V with channel length from 10 µm down to 5 µm by transmission line method. Extracted 2∆L, the difference between mask channel length and effective channel length, from GI type A, B, and C are 0.78 µm, 0.87 µm, and 1.05 µm, respectively. The IGZO TFTs with higher GI power show better TFT uniformity than lower power GI without notable negative Vth shift and non-uniformity even with shorter channel length from 10 µm down to 3 µm by minimizing hydrogen diffusion into IGZO (Fig. 2). The IGZO TFTs with lower GI power show better stability under PBTS due to more hydrogen diffusion into IGZO. On the other hands, the IGZO TFTs show better stability under both PBTS and NBTS with higher GI temperature than lower temperature GI due to more hydrogen diffusion into IGZO (Fig. 3). Therefore, high power/high temperature GI is preferred for high-resolution mobile/VR displays considering short channel length effect and low power/high temperature GI is preferred for gate driver integrated OLED TVs considering stability, especially PBTS. Figure 1

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

Hydrogen sensitivity in indium-tin-zinc-oxide (ITZO) dual gate (DG) thin-film transistors (TFTs) has fundamentally limited their commercial viability despite superior electron mobility. This work addresses this challenge through systematic optimization of SF6 plasma treatment, demonstrating its effectiveness in suppressing hydrogen diffusion-induced degradation. Comprehensive analysis reveals that increased SF6 plasma power significantly reduces oxygen vacancy and hydrogen content in ITZO channels. Consequently, TFT performance shows critical improvements: threshold voltage shifts positively from -4.25 V to 0.32 V, subthreshold swing tightens from 0.38 V/dec to 0.20 V/dec, and field-effect mobility undergoes a controlled reduction (38.25 cm² /V• s to 32.53 cm² /V• s). Most crucially, electrical stability under various stress conditions shows dramatic enhancement: The threshold voltage shift for the positive bias temperature stress (PBTS) test decreased from -8.58 V to -2.36 V, negative bias temperature stress (NBTS) test decreased from -0.79 V to -0.07 V, which is almost negligible, and negative bias illumination stress (NBIS) test decreased from -4.76 V to -0.68 V. These findings establish SF6 plasma power engineering as a manufacturable pathway to simultaneously achieve high performance and unprecedented operational stability in ITZO DG TFTs for next-generation displays.

Numerous solution-processed dielectrics were studied in metal oxide thin film transistors (TFTs) to understand their potential application in flexible display technology. A series of dielectrics was synthesized and systematically formulated to deposit organic gate insulating thin film layers that demonstrate low leakage current (≤10−8 A/cm2 at 2 MV/cm), high breakdown voltages (>150 V), film flexibility, photopatternability (5–10 µm via hole size), increased temperature stability (up to temperatures of 300 °C), and resistance to common chemicals used in the indium gallium zinc oxide (IGZO) TFT fabrication process. In particular, surface modification improved the stability of bottom-gate organic gate insulators during the sputtering, patterning, and annealing processes for the IGZO active layer on the dielectric surface. The best IGZO TFT performance was achieved when certain Polyera organic gate insulators were incorporated in top-gate top-contact IGZO TFT devices, yielding excellent mobility (∼15 cm2/V·s), V th ∼ 0 V, negligible hysteresis, sharp sub-threshold swing (∼300 mV/dec), and good bias temperature stress stability. When combined with polymer substrates such organic gate insulators yield truly flexible IGZO TFTs compatible with large-scale production methods.

Oxide thin film transistors (TFTs) have attracted much attention for next-generation electronics because of their superior performance compared with conventional a–Si TFTs such as high mobility and optical transmittance in the visible light.1 Some display manufacturing companies have already manufactured oxide TFTs based products, but there are some issues remained for oxide TFTs to be used for flexible displays. One of the issues is the high-temperature annealing process (> 300°C). Due to low thermal durability, flexible substrates cannot be processed in high temperatures.2-3 In this study, we propose various researches to lower the processing temperatures in oxide TFTs: photocatalytic reactions of titanium dioxide (PRT) and rotating magnetic field (RMF) treatment. In addition, we suggest ethyl cyanoacrylate (ECA) based instant glue (IG) as a new material for the passivation layers of oxide TFTs with low processing temperature. Photocatalytic Reaction of Titanium Dioxide (PRT) In this study, we fabricate indium–zinc oxide (IZO) TFTs using PRT. The hydroxyl radicals are generated by reaction between titanium dioxide (TiO2) and water molecules during UV irradiation. These hydroxyl radicals decompose the 2-methoxyethanol (2ME; one of the representative solvents) into smaller organic molecules. The decomposed 2ME has low boiling points and molar masses compared with non-PRT treated 2ME. Therefore, PRT treatment not only provides superior electronic devices caused by less defect sites in the oxide channel layers, but also allows low temperature process at 230°C. Additionally, since TiO2 particles can generate hydroxyl radicals permanently under UV irradiation, the PRT treated IZO TFTs show improved electrical characteristics even after four times recycling of TiO2. Rotating magnetic field (RMF) treatment In this work, we fabricate indium–gallium–zinc oxide (IGZO) TFTs by RMF treatment at a low temperature of 150°C. For RMF treatment, IGZO films are exposed to periodically rotating magnetic field and thermal energy of 150°C. The magnetic field and thermal energy simultaneously facilitate the interaction and attraction of metal and oxygen atoms leading to formation of M–O bonds in IGZO films. As a result, RMF treated IGZO TFTs exhibited improved electrical performances and positive bias stress (PBS) characteristics compared with those of IGZO TFTs treated by only thermal annealing process at 300°C. Instant Glue (IG) Passivation We introduce IG as a novel material for the passivation layer of IGZO TFTs. The ECA-based IG is a moisture-curing adhesive, which is liquid at room temperature and cures rapidly by reacting with moisture in atmosphere. As it is solidified rapidly at room temperature, it has shorter process time than that of conventional organic materials; the IG passivation layer is prepared successfully just for 1 min at 150°C. The IG passivation layer can modify the chemical stoichiometry of IGZO films and prevent any interaction between the back surface of the IGZO TFT and ambient gas. Therefore, the IGZO TFTs with an IG passivation layer show improved electrical characteristics and reliability compared to those without passivation layer. References Jae Won Na, You Seung Rim, Hee Jun Kim, Jin Hyeok Lee, Seonghwan Hong, and Hyun Jae Kim, ACS Appl. Mater. Interfaces 9, 35, 29849 (2017).Hua Xu, Dongxiang Luo, Min Li, Miao Xu, Jianhua Zou, Hong Tao, Linfeng Lan, Lei Wang, Junbiao Peng, and Yang Cao, J. Mater. Chem. C 2, 7, 1255 (2014).Seonghwan Hong, Sung Pyo Park, Yeong-gyu Kim, Byung Ha Kang, Jae Won Na, and Hyun Jae Kim, Scientific Reports 7, 1, 16265 (2017). Figure. Schematics of various techniques to lower the processing temperatures for oxide TFTs, (a) photocatalytic reaction of titanium dioxide, (b) rotating magnetic field treatment, (c) instant glue passivation. Figure 1

This work evaluates the performance of Neuromorphic architecture for accessing Static Random Access Memory (SRAM) in an asynchronous manner. Spike-Timing Dependent Plasticity (STDP) learning algorithm for updating the synaptic weights values in the SRAM module. Input, output, and synaptic weight values are transmitted to/from the chip using a common communication protocol based on the Address Event Representation (AER). Memory array an important block in digital system. Bassically SRAM is used for increasing speed of the processor. Which is mostly connected between the DRAM and microprocessor. SRAM serves as cache memory which stores the information and losses its data without power. We may design the SRAM using 4T, 6T, 8T....for storing one bit. Sense amplifier is used to perform read and write operation. Instead of using sense amplifier we use the neural network concept. Synapse is connected between the SRAM and neuron. The minute gap across which nerve impulses pass from one neurone to the next, at the end of a nerve fiber. Each neurone has an enlarged portion the cell body, containing the nucleus; from the body extend several process through which impulses enter from their branches. A longer process, the nerve fiber, extends outwards and carries impulse away from the cell body. This is normally unbranched except at the nerve ending. This consumes less power than the normal memory circuit.

Amorphous oxide semiconductors, especially indium gallium zinc oxide (IGZO), have been widely studied and obtained significant progress in flexible thin-film transistors (TFTs) due to the high carrier mobility and low deposition temperature. However, a further annealing step is generally required to activate electrical properties and improve the device performance, which limited their applications in flexible electronics. In this study, we achieved flexible TFTs and arrays using co-sputtered IGZO and indium tin oxide (ITO) as channels deposited at room temperature without post-annealing. It was found that better transistor switching properties could be effectively achieved by regulating the sputtering power of ITO in the co-sputtered deposition. The device performance is comparable to that of the conventional oxide TFTs with high annealing temperatures (⩾300 °C), exhibiting a high saturation mobility (μ sat) of 15.3 cm2 V−1s−1, a small subthreshold swing (SS) of 0.21 V dec−1, and a very high on–off ratio (I on/off) of 1011. In addition, a 12 × 12 flexible TFT array was achieved with uniform performance owing to the low-temperature processing advantage of this technique. The flexible TFTs exhibited robust mechanical flexibility with a minimum bending radius of 5 mm and bending cycles up to 1000. Furthermore, an inverter based on co-sputtered IGZO and ITO was demonstrated with the maximum gain of 22. All these achievements based on the proposed TFTs without post-annealing process are expected to promote the applications in advanced flexible displays and large-area integrated circuits.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

Nowadays, active matrix organic light emitting diodes (AMOLED) with higher resolution and narrower bezel can be achieved by using integrated gate driver on array (GOA) technology. In order to reduce the bezel width of displays more effectively, the width of GOA circuit needs to be reduced. In this paper, we study the transfer characteristics and output characteristics of dual-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) by comparing with single gate TFTs. Dual gate TFTs exhibit high mobility and good PBTS reliability on Gen. 4.5 glass. Subsequently, we propose a gate driver on array (GOA) circuit by using dual gate TFTs to narrowing the width of GOA circuit layout. The GOA circuit was operated for 1020h under accelerating test conditions of 60 degrees Celsius, indicating high reliability of this GOA circuit.

In this work, we have fabricated thin film transistors (TFTs) from a solution-based indium gallium zinc oxide (IGZO) and single-walled carbon nanotube (SWNT) blend by varying SWNT concentration. In order to improve electrical performances of IGZO TFT, SWNTs were used as carrier transport rods. We found out that the saturation field effect mobility (μsat) and on/off current ratio varied when the SWNT concentration changed. The concentration of SWNT in the solution is a critical parameter to control the electrical performances of IGZO TFT. The optimized performance of IGZO TFT with 0.04 wt.% SWNT concentration is as follows: μsat of about 0.11 cm2/Vs, an on/off current ratio of ∼ 105, threshold voltage (Vth) of − 2.5 V, and a subthreshold slope (S-factor) of 4.1 V/decade.

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 /spl mu/m CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

Serious reliability concerns of Static Random Access Memories (SRAMs) in nanometer technologies are the increased process variations as well as the various aging mechanisms. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) phenomena are the main factors related to the aging reliability reduction. This degradation affects speed, operating voltages, memory cell noise margins and sense amplifier input offset voltage. Thus, it is imperative to develop design techniques for aging tolerance that will provide the ability to sense aging levels, predict upcoming failures in the memory and early react to retain the reliable operation. In this work, a circuit for the periodic aging monitoring in SRAM sense amplifiers and memory cells is presented.