High performance sense amplifier circuit for low power SRAM applications

A high-speed sense amplifier capable of static random access memory (SRAM) applications has been developed in this work. The proposed sense amplifier can work at 1GHz with voltage as low as 1.8 V. Restated, the proposed sense amplifier can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Simulated results show that the proposed sense amplifier has 50/spl sim/87.5 % speed improvement compared to the conventional sense amplifiers.

DRAM industry has gained most of the interest in the memory chip industry in the last decades for its high density (due to its simple structure) and lower power consumption. As the density of DRAM chips increased, the bit-line parasitic capacitances increased and many problems appeared such as increased power consumption and larger read/write access times which gave great attention to improve the design of the CMOS sense amplifier used in the memory chip for its great effects on memory access time, overall memory power dissipation and chip density. In this paper, we introduce one of the most effective solutions to increase the performance of the advanced high density DRAMs by replacing the sense amplifier circuit with a specially designed logic buffer circuit based on Resonant Tunneling Diode (RTD) that can be fabricated in Nano-scale and exhibit higher operation speed with lower power consumption and higher chip density. The proposed design improves the Power Delay Product (PDP) by about 36% compared with that in conventional RTD-CMOS sense amplifier and 15% compared with that in conventional CMOS sense amplifier. The 45nm CMOS technology is used in this paper.

DRAM chip industry became one of the most researchers' interests nowadays for its simple structure and low power consumption. As the density of DRAM chips increased, many problems occurred that affected the DRAM performance. One of these problems is the increase in the bit-line parasitic capacitance values. These large values slow down the reading operation of the cell and increase the consumed power. This problem gave a great attention to improve the performance of the sense amplifier circuit that is used in the reading operation in the DRAM cell for its great effect on both DRAM access times and overall power consumption. In this paper, we introduce an alternative circuit architecture for the CMOS sense amplifier. This proposed circuit architecture is a specially designed logic buffer using a Resonant Tunneling Diode (RTD) that can be fabricated in silicon nano-electronics. The proposed design exhibits higher read operation speed, lower power consumption, full noise margin and higher chip density. The Power Delay Product (PDP) is improved by about 62% compared with that in the conventional CMOS sense amplifier and by about 70% compared with that in the conventional RTD-CMOS sense amplifier. The CMOS technology used in this paper is 45nm technology.

Thin-film transistor (TFT) not only is the backbone of display technology, but also brings in fancy applications in the area of flexible electronics. TFT-based flexible circuit design however faces various challenges, such as unipolar devices and severe nonuniformity. In this paper, a sense amplifier based on dual-gate indium-gallium-zinc oxide (IGZO) TFTs is proposed for TFT-based static random access memory (SRAM) circuits. The pull-up transistors in the proposed sense amplifier are implemented with dual-gate TFTs while the pull-down transistors are implemented with conventional bottom-gate TFTs. By tuning the top gate of the pull-up transistors to achieve a negative threshold voltage as well as employing a specialized strength- adaptive pull-up structure, the proposed sense amplifier aims to reduce the offset voltage, sensing delay, and sensing power consumption simultaneously. Compared to the state-of-the-art IGZO-based sense amplifier, the proposed sense amplifier achieves up to 66.1% lower offset voltage, 68.9% shorter sensing delay, 72% dynamic power savings, and 66.3% leakage power savings.

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

A newly proposed Double Latch Pre-charge Sense Amplifier (DLPSA) is introduced in the embedded non- volatile memory design for the wireless application, especially for smart cards with wireless & contactless feature, e.g., bank cards (wireless credit cards). This DLPSA has been implemented in both SMIC 0.18im and 0.13im process of ROM IPs. Comparing with the conventional sense amplifier, DLPSA has lower current consumption, lower minimum voltage and wider voltage range. This novel sense amplifier/driver structure is capable of restoring the full signal swing effectively. On top of that, its minimum VDD equates to low power consumption at VDDMIN.

Magnetic tunnel junction (MTJ) device, a nonvolatile spintronics device, draws wide attention for its low current drive, non-volatility, small size, infinite erasure, and low standby power. It is widely used in magnetic random-access memory (MRAM) or embedded in CMOS logical circuits. In this paper, a novel high speed, low resource and non-volatile MTJ-CMOS hybrid logical circuit structure is proposed, which consists of Multi-Voltage controlled Multi-Write (MVMW) write circuit and High-Speed Sense Amplifier (HSSA) circuit. The MVMW write circuit enhances the write speed by shortening the critical path while achieving two independent write controls of the MTJs. Also, a voltage comparator sense amplifier is employed to increase the read speed (about 110ps). By using a dynamic compact MTJ model and 55 nm CMOS design kit, we designed a circuit architecture which can be used to form all kinds of logical computations. An AND/NAND logical is used to demonstrate functionality of the architecture and compared it with a traditional MTJ-CMOS hybrid circuit. The proposed non-volatile MTJ-CMOS hybrid circuit uses only 62.5% of resources, achieving a 4.37X write speed and a 2.64X read speed. The overall average speed increases 3.12 times with similar power consumption. Moreover, it is compatible for asynchronous circuits design.

Design of RRAM with high storage capacity and high reliability for IoT applications

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.

In the era of big data, massive data requires processing efficiently. However, the limited data bandwidth between the memory and the processor in conventional computer systems could not meet the requirement of data transferring. Computing in-memory has been considered an effective solution to address this problem. In this paper, based on the spin transfer torque-magnetic random access memory (STT-MRAM), a computing in-memory architecture with as few peripheral circuits as possible is proposed. This computing in-memory architecture gives the specific reference cell so that two rows in one array can be activated simultaneously to perform bitwise logic operations, such as OR/NOR and AND/NAND. In addition, with technology scaling down, STT-MRAM suffers from high sensitivity to process variation, which results in more device mismatch in a sense circuit. Additionally, the negative bias temperature instability (NBTI) seriously affects the life of PMOS transistors used in a sense circuit. In this paper, a high-reliability sense amplifier for computing in-memory with STT-MRAM is proposed. By using two self-enabled switching transistors, the proposed sense amplifier not only can decrease the NBTI effect on PMOS transistors but also can achieve a low sensing error rate. Using a CMOS 40[Formula: see text]nm design-kit and an accurate compact model of the STT magnetic tunnel junction (MTJ), mixed transient and statistical simulations have been present to demonstrate the functionality and performance of the proposed circuits.

As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various and segmented system to fill the gap between the current memory systems in terms of the cost and performance. The nonvolatile memory will upgrade the current memory subsystems and enable the stable system architectures that retain their state even when power is off. The emerging memories will not directly replace the existing memory (DRAM and Flash memory) but will make a new memory class. The attributes of STT-MRAM can lead to adopt in-memory computing architectures for the embedded memory solution SoC. In these circumstances, the accurate and scalable model of magnetic tunnel junction (MTJ) is required to accelerate the commercialization of STT-MRAM. In this thesis, after the MTJ basics is introduced as a storage element and the magnetic dynamics to utilize the electron spins as wells as the electron charges, the parallel and anti-parallel magnetization configuration is explained in terms of the band structure to understand the basic operation of the MTJ in memory cell. To demonstrate the viability of MTJ as a memory cell, the switching mechanism, reading/writing scheme, and some important parameters in STT-MRAMs such as TMR (Tunneling Magnetoresistance), Switching current (Ic), and Thermal Stability (Δ) are investigated. As a test vehicle of the technology, a set of RAM is designed in this research to show its efficiency and advantages of MTJ memory cell. As a first step of the design, the scalable model of a MTJ that accurately depicts the spin-transfer torque dynamic switching behavior of a MTJ is verified along with its bias voltage and Temperature dependency. The model integrates the physical models of static and dynamic behaviors; many experimental parameters are provided to see the process variations, especially temperature and bias voltage perspective. Based on the verified model, a set of RAM circuit is designed, and the designed STT-MRAM circuit's behavior and performances are analyzed to find the optimum tunnel magnetoresistance (TMR) ratio and switching performance. Of the compact model of the CoFeB/MgO PMA-MTJ (perpendicular magnetic anisotropy MTJ). The whole circuit was designed in a standard 45nm CMOS technology using MTJ. The measurement shows that the switching delay of MTJ increases by 5.5ns with growing tunnel barrier oxide (MgO) thickness from 0.85nm to 1.15nm. A bit longer delay for writing is observed as expected. The simulation shows a trade-off between memory access time and MTJ area as the switching delay of MTJ decreases by 6.5ns when the MTJ area increases from 1010nm to 4040nm. For reading operation of the memory, the conventional sense amplifier circuit is employed to detect the stored bit-cell. In the reading peripheral circuits including sense amplifier, the fixed reference voltage (0.9V) is used to simplify the analysis. The reading operation and peripheral block of memory circuits is verified successfully with read access time of 1.47ns.--Author's abstract

The transistor offset from sense amplifiers affects the sensing performance in dynamic random-access memory (DRAM). Although various offset-compensation methods are available, the voltage mismatch remains large, and some methods are susceptible to timing variation. To improve the compensation effect and stability, we propose a current-mirror and switching-point compensation sense amplifier. The amplifier compensates one bit-line voltage to the switching point of an inverter and adjusts the other bit-line by a current mirror during compensation. The configuration is robust against timing variation. Moreover, the voltage of complementary bit line considerably changes due to the high gain of the switching point. Simulation results show that the voltage mismatch can be improved by 90% compared with that of a boosted reference voltage sense amplifier. In addition, the increased bit-line differential voltage can improve the sensing speed. At a low supply voltage of 0.75 V, the sensing yield improves by 11% compared with that of a boosted reference voltage sense amplifier and by 16% compared with that of an offset-cancellation sense amplifier.

Researchers have investigated several different sense amplifiers’ yield and other quantitative features. Amplification is required for various power-saving methods, including the sleep transistor, the sleep stack, the sleepy keeper, and others. This study aims to evaluate how much energy is consumed by the many different sense amplifier topologies. Simulations have shown that adopting a sleep transistor approach can significantly reduce the amount of power lost even while operating at 1.2V.