Enhancement of DRAMs performance using resonant tunneling diode buffer

DRAM chip industry became one of the most researchers' interests nowadays for its simple structure and low power consumption. As the density of DRAM chips increased, many problems occurred that affected the DRAM performance. One of these problems is the increase in the bit-line parasitic capacitance values. These large values slow down the reading operation of the cell and increase the consumed power. This problem gave a great attention to improve the performance of the sense amplifier circuit that is used in the reading operation in the DRAM cell for its great effect on both DRAM access times and overall power consumption. In this paper, we introduce an alternative circuit architecture for the CMOS sense amplifier. This proposed circuit architecture is a specially designed logic buffer using a Resonant Tunneling Diode (RTD) that can be fabricated in silicon nano-electronics. The proposed design exhibits higher read operation speed, lower power consumption, full noise margin and higher chip density. The Power Delay Product (PDP) is improved by about 62% compared with that in the conventional CMOS sense amplifier and by about 70% compared with that in the conventional RTD-CMOS sense amplifier. The CMOS technology used in this paper is 45nm technology.

Representatively, memory has been limitedly used in advances, such as Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), and Flash Memory. However, nowadays, memory is widely used in smartphones, automobiles, and the Internet of Things (IoT) in everyday electronic devices. Furthermore, there is currently a growing need for high-density memory in terms of size and energy efficiency due to increasing data and computation demands. Non-volatile Memories (NVMs) are promising candidates for achieving fast processing speeds, high data storage density, and energy efficiency because emerging NVMs (STT-MRAM, PCM, ReRAM) offer more of these advantages compared to conventional memory. Among NVMs, ReRAM boasts advantages such as non-volatility, fast write times, a larger resistance ratio (R-Ratio), and low power consumption. Despite the numerous advantages provided by RRAM, significant challenges still need to be addressed, such as resistance variations during fabrication and resistance drift during operation. This variation, which affects retention and the cycle, can lead to resistance degradation, resulting in a reduced the R-ratio (RHRS/RLRS) of ReRAM. Additionally, this resistance variation affects reference cells composed of ReRAM unit cells. Furthermore, resistance degradation can also affect the Bit-line voltage (VBL) during the read operation. Therefore, a low VBL is necessary to prevent this. However, maintaining a low VBL raises concerns about margin and delay. The proposed new sense amplifiers effectively address this variation. This first study proposes a reliable current sense amplifier assisted with dynamic reference (DR-CSA) to enhance sensing margin and robustness. The proposed sensing circuit detects a slight voltage change through capacitive coupling and adjusts the reference current based on the cell states (RHRS ,RLRS) to enhance the sensing margin. This second study introduces a novel time-based sensing (TBS) scheme for enhancing the speed and robustness during the operation and extends from single-level cells (SLC) to multi-level cells (MLC). In the proposed time-based sensing scheme, the bit line (BL) current is converted into a time delay based on cell states using the current-to-time converter (CTC). The resulting distinct time delays are compared to generate digital data. Additionally, The proposed sensing scheme executes sensing operations without using both a reference array and reference generator for reference current or reference voltage, which are required in a conventional current sense amplifier (CSA) or voltage sense amplifier (VSA). The last study introduces a novel hybrid cell-to-cell, referenceless sensing scheme. Since the proposed novel hybrid sensing scheme directly compares cell-to-cell, it requires no analog reference or generator, as is used in conventional voltage-mode schemes or current-mode schemes. Furthermore, the proposed scheme reads 2-bit data during the sensing process simultaneously and is compatible with two load modes: both voltage mode and current mode.

A high performance sense amplifier (SA) circuit for low power SRAM applications is presented in this paper. The transistor stage number of the proposed SA from VDD to GND is reduced for fast low voltage operation. Thus the proposed sense amplifier which is implemented in 0.35 /spl mu/m CMOS process can work at 100 MHz with voltage as low as 1V. The improvement of sensing delay is 6-14% for various output loading. As the proposed SA works at 3.3 V, the simulations show that this design has 14% and 63% power delay product improvement over the prior art and conventional sense amplifier, respectively.

A newly proposed Double Latch Pre-charge Sense Amplifier (DLPSA) is introduced in the embedded non- volatile memory design for the wireless application, especially for smart cards with wireless & contactless feature, e.g., bank cards (wireless credit cards). This DLPSA has been implemented in both SMIC 0.18im and 0.13im process of ROM IPs. Comparing with the conventional sense amplifier, DLPSA has lower current consumption, lower minimum voltage and wider voltage range. This novel sense amplifier/driver structure is capable of restoring the full signal swing effectively. On top of that, its minimum VDD equates to low power consumption at VDDMIN.

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

As the memory market becomes more diverse, the conventional memory hierarchies composed of Flash memory, DRAM and SRAM are now being asked to have various and segmented system to fill the gap between the current memory systems in terms of the cost and performance. The nonvolatile memory will upgrade the current memory subsystems and enable the stable system architectures that retain their state even when power is off. The emerging memories will not directly replace the existing memory (DRAM and Flash memory) but will make a new memory class. The attributes of STT-MRAM can lead to adopt in-memory computing architectures for the embedded memory solution SoC. In these circumstances, the accurate and scalable model of magnetic tunnel junction (MTJ) is required to accelerate the commercialization of STT-MRAM. In this thesis, after the MTJ basics is introduced as a storage element and the magnetic dynamics to utilize the electron spins as wells as the electron charges, the parallel and anti-parallel magnetization configuration is explained in terms of the band structure to understand the basic operation of the MTJ in memory cell. To demonstrate the viability of MTJ as a memory cell, the switching mechanism, reading/writing scheme, and some important parameters in STT-MRAMs such as TMR (Tunneling Magnetoresistance), Switching current (Ic), and Thermal Stability (Δ) are investigated. As a test vehicle of the technology, a set of RAM is designed in this research to show its efficiency and advantages of MTJ memory cell. As a first step of the design, the scalable model of a MTJ that accurately depicts the spin-transfer torque dynamic switching behavior of a MTJ is verified along with its bias voltage and Temperature dependency. The model integrates the physical models of static and dynamic behaviors; many experimental parameters are provided to see the process variations, especially temperature and bias voltage perspective. Based on the verified model, a set of RAM circuit is designed, and the designed STT-MRAM circuit's behavior and performances are analyzed to find the optimum tunnel magnetoresistance (TMR) ratio and switching performance. Of the compact model of the CoFeB/MgO PMA-MTJ (perpendicular magnetic anisotropy MTJ). The whole circuit was designed in a standard 45nm CMOS technology using MTJ. The measurement shows that the switching delay of MTJ increases by 5.5ns with growing tunnel barrier oxide (MgO) thickness from 0.85nm to 1.15nm. A bit longer delay for writing is observed as expected. The simulation shows a trade-off between memory access time and MTJ area as the switching delay of MTJ decreases by 6.5ns when the MTJ area increases from 1010nm to 4040nm. For reading operation of the memory, the conventional sense amplifier circuit is employed to detect the stored bit-cell. In the reading peripheral circuits including sense amplifier, the fixed reference voltage (0.9V) is used to simplify the analysis. The reading operation and peripheral block of memory circuits is verified successfully with read access time of 1.47ns.--Author's abstract

A low-voltage high-speed bulk-CMOS SRAM that operates over 100MHz at 0.5V, for the first time, is proposed. A novel 8-transistor (8T) memory cell with a complementary read port (C-RP) improves the read speed by enabling differential bit-line sensing, while the conventional 8T SRAM drives the bit line with a single read port (S-RP). The cell layout of the C-RP SRAM has point symmetry and a small area overhead (1.4x) compared with the conventional 6T SRAM cell, without any additional layers. The read delay and the delay variation at 0.5V were reduced by 52% and 54%, respectively, compared with the conventional S-RP 8T cell. A suspended bit-line read (SBLR) scheme is also applied to the read circuit in order to eliminate the leakage current from the unselected cells, which is an inevitable issue for a C-RP 8T cell with a conventional voltage sense amplifier (VSA). The simulated results of 1 Kbit SRAM in a 65-nm standard bulk-CMOS technology demonstrated 150-MHz operating frequency at 0.5-V single Vdd without any assist techniques. The power-delay product was reduced by 64% compared with the conventional S-RP 8T This SRAM was implemented in test chips using 65-nm and 40-nm bulk-CMOS technologies.

Sense amplifiers play an important role in memories like Dynamic Random Access (DRAM) and Static Random Access (SRAM) for read operations. Sense amplifier is one of the peripheral circuits in memories that are placed in each column of the memory array. A sense amplifier compares the bit line voltage and its complement, and then amplifies it to rail to rail output voltages. In this project, several latch type sense amplifier have been designed and simulated using 90nm CMOS technology with a supply voltage of 1.2V. Sensing delay is one of the important factors in sense amplifier design and it will be calculated for all sense amplifiers by performing voltage scaling.

This paper presents a design and detailed FFT analysis for CMOS sense amplifiers. Sense amplifiers in association with semiconductor memories are the key elements in defining the overall performance of CMOS memories. The presented design is implemented using C5 process technology using BSIM-4 Spice models. The design includes circuit and operation descriptions, transient signal analysis, FFT analysis, also evaluation of magnitude, phase, and group delay is done at range frequency range from 100 MHz to 10 THz. The paper also presents a physical design and interfacing logic for interfacing CMOS Memory arrays to Sense amplifiers and related control circuits.

A high-speed sense amplifier capable of static random access memory (SRAM) applications has been developed in this work. The proposed sense amplifier can work at 1GHz with voltage as low as 1.8 V. Restated, the proposed sense amplifier can be used in memory units, as a line receiver and as a restoring element for small-swing logic. Simulated results show that the proposed sense amplifier has 50/spl sim/87.5 % speed improvement compared to the conventional sense amplifiers.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

The fully π-conjugated donor-acceptor hybrid polymers Fl-TPA, Fl-TPA-TCNE, and Fl-TPA-TCNQ, which are composed of fluorene (Fl), triphenylamine (TPA), dimethylphenylamine, alkyne, alkyne-tetracyanoethylene (TCNE) adduct, and alkyne-7,7,8,8-tetracyanoquinodimethane (TCNQ) adduct, were synthesized. These polymers are completely amorphous in the solid film state and thermally stable up to 291-409 °C. Their molecular orbital levels and band gaps vary with their compositions. The TCNE and TCNQ units, despite their electron-acceptor characteristics, were found to enhance the π-conjugation lengths of Fl-TPA-TCNE and Fl-TPA-TCNQ (i.e., to produce red shifts in their absorption spectra and significant reductions in their band gaps). These changes are reflected in the electrical digital memory behavior of the polymers. Moreover, the TCNE and TCNQ units were found to diversify the digital memory modes and to widen the active polymer layer thickness window. In devices with aluminum top and bottom electrodes, the Fl-TPA polymer exhibits stable unipolar permanent memory behavior with high reliability. The Fl-TPA-TCNE and Fl-TPA-TCNQ devices exhibit stable unipolar permanent memory behavior as well as dynamic random access memory behavior with excellent reliability. These polymer devices were found to operate by either hole injection or hole injection along with electron injection, depending on the polymer composition. Overall, this study demonstrated that the incorporation of π-conjugated cyano moieties, which control both the π-conjugation length and electron-accepting power, is a sound approach for the design and synthesis of high-performance digital memory polymers. The TCNE and TCNQ polymers synthesized in this study are highly suitable active materials for the low-cost mass production of high-performance, polarity-free, programmable, volatile, and permanent memory devices that can be operated with very low power consumption, high ON/OFF current ratios, and high reliability.

Increased process variation and reduced operating voltage present two of the main challenges in using sense amplifiers for small geometry bulk CMOS process technology. This fact coupled with the need to increase on-chip memory to reduce traffic on the bus and increase performance creates the need for a robust and reliable sense amplifier - a differentiating factor in memory area, power, and speed. We present a detailed study of the Voltage Latched Sense Amplifier (VLSA) and the Current Latched Sense Amplifier (CLSA) design in 28nm industry standard process technology [1][2]. We present results on how the two sense amplifier behave for the two design topology for low power (LP) process technology optimized for mobile low leakage application and the second one is high performance High Performance (HP) applications. Detailed Spice simulation with statistical models and Monte Carlo simulations is utilized to compare the two designs for active power, leakage power, speed, and area. Our study shows that VLSA performs better than CLSA - being 67% faster, 35% smaller area, and similar active power for the LP. The VLSA also performed better than the CLSA is the HP technology as well. The sensitivity to temperature for the LP technology node was more at high voltage but for the HP process the lower voltage perform worse.

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

The trend of decreasing device size and increasing chip densities involving several hundred millions of transistors per chip has resulted in tremendous increase in design complexity. Low power SRAMs are essential in today's demand as they are preferred as on chip memories with read write stability. The primary design challenge related to the conventional six-transistor (6T) memory cells is the conflicting set of requirements for achieving read data stability and write ability. The proposed seven-transistor SRAM cell for very high density and low power embedded applications as well as for stand-alone SRAM applications. It uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell. This paper presents a method based on multi-Vt to increase read, write stability and reduce the total leakage power dissipation of SRAMs while maintaining their performance. The proposed method is based on the observation that read and write delays of a memory cell in an SRAM block depend on the physical distance of the cell from the sense amplifier and it is also depend on Vt. The Cadence Virtuoso simulation in standard 45nm CMOS technology confirms all results obtained for this paper.