Comparative analysis of sense amplifiers for memories

<p>Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology.</p>

1kb static random access memory (SRAM) is designed and tested for correct read and write operation. Novel Sense Amplifier (SA) circuit for 1kb SRAM are presented and analysed in this paper. Sense amplifier using decoupled latch with current controlled architecture is proposed and compared with Current controlled latch SA using 90nm CMOS technology. Delay and power dissipation in proposed SA is 21.5% and 18.5% less than that of current controlled SA. The maximum operating frequency of the SRAM is found as 1.25GHz.

Increased process variation and reduced operating voltage present two of the main challenges in using sense amplifiers for small geometry bulk CMOS process technology. This fact coupled with the need to increase on-chip memory to reduce traffic on the bus and increase performance creates the need for a robust and reliable sense amplifier - a differentiating factor in memory area, power, and speed. We present a detailed study of the Voltage Latched Sense Amplifier (VLSA) and the Current Latched Sense Amplifier (CLSA) design in 28nm industry standard process technology [1][2]. We present results on how the two sense amplifier behave for the two design topology for low power (LP) process technology optimized for mobile low leakage application and the second one is high performance High Performance (HP) applications. Detailed Spice simulation with statistical models and Monte Carlo simulations is utilized to compare the two designs for active power, leakage power, speed, and area. Our study shows that VLSA performs better than CLSA - being 67% faster, 35% smaller area, and similar active power for the LP. The VLSA also performed better than the CLSA is the HP technology as well. The sensitivity to temperature for the LP technology node was more at high voltage but for the HP process the lower voltage perform worse.

Sense amplifiers have of late become an important class of circuits due the major role they play in the design of low voltage memory design. It is an active circuit capable to enhance signal promulgation from the selected cell in a memory array to peripheral logic circuits and changes the random logic levels on a bit-line to the digital logic levels of the Boolean circuits in the periphery. In this paper the memristor loaded cross-coupled differential voltage sense amplifier is proposed as a possible surrogate for CMOS based cross coupled differential amplifier to reduce the area size, increase the gain and the speed of operation. With the exponential increase in the memory array sizes the bit line capacitance and cell-access resistance has become very large and this merger conjoined with the further reduction in output energy produced by the cell during reading will aggregate in the generation of a small signals from each selected cell. These small signals will make it difficult for data value detection and determination and will cause a prolonged latency times. To enhance performance speed and to provide signals that can be properly read as logic 0/1 many sense amplifiers have been designed to give faster sensing by responding to low voltage swings. To improve the gain of the sense amplifier by increasing the load resistance the memristor cells is in cooperated in amplifier. The memristor was selected as it propound reduced leakage current, populate less space area and because of quantization of conductance using memristive state allows for easy adjustability of the sense amplifier. The proposed memristor loaded sense amplifier was compared to the conventional CMOS based cross-coupled sense amplifier.

This paper involved the design and analysis of multi-threshold voltage CMOS (MTCMOS) current sense amplifier focusing on optimizing power and time delay. In this work the basic 6T SRAM structure was chosen and the simulation is implemented using ADS programs. The key to low power operation in the SRAM data path is to reduce the signal swings on the bit lines and the data lines. The power dissipation and delay of the sense amplifier circuit can be further reduced by using several low power and high speed techniques like MTCMOS. This technique can be used for solving the leakage power dissipation problem in the higher technology design. Simulated results show the current mode sense amplifier with MTCMOS technology has 0.82ns time delay and 0.395μW power dissipation. The designs and simulations in 0.25μm CMOS technology with supply voltage equal to 1.8 V have been carried out to evaluate the efficiency of the current mode sense amplifier with MTCMOS technique proposed.

Thin-film transistor (TFT) not only is the backbone of display technology, but also brings in fancy applications in the area of flexible electronics. TFT-based flexible circuit design however faces various challenges, such as unipolar devices and severe nonuniformity. In this paper, a sense amplifier based on dual-gate indium-gallium-zinc oxide (IGZO) TFTs is proposed for TFT-based static random access memory (SRAM) circuits. The pull-up transistors in the proposed sense amplifier are implemented with dual-gate TFTs while the pull-down transistors are implemented with conventional bottom-gate TFTs. By tuning the top gate of the pull-up transistors to achieve a negative threshold voltage as well as employing a specialized strength- adaptive pull-up structure, the proposed sense amplifier aims to reduce the offset voltage, sensing delay, and sensing power consumption simultaneously. Compared to the state-of-the-art IGZO-based sense amplifier, the proposed sense amplifier achieves up to 66.1% lower offset voltage, 68.9% shorter sensing delay, 72% dynamic power savings, and 66.3% leakage power savings.

The transistor offset from sense amplifiers affects the sensing performance in dynamic random-access memory (DRAM). Although various offset-compensation methods are available, the voltage mismatch remains large, and some methods are susceptible to timing variation. To improve the compensation effect and stability, we propose a current-mirror and switching-point compensation sense amplifier. The amplifier compensates one bit-line voltage to the switching point of an inverter and adjusts the other bit-line by a current mirror during compensation. The configuration is robust against timing variation. Moreover, the voltage of complementary bit line considerably changes due to the high gain of the switching point. Simulation results show that the voltage mismatch can be improved by 90% compared with that of a boosted reference voltage sense amplifier. In addition, the increased bit-line differential voltage can improve the sensing speed. At a low supply voltage of 0.75 V, the sensing yield improves by 11% compared with that of a boosted reference voltage sense amplifier and by 16% compared with that of an offset-cancellation sense amplifier.

Sense amplifiers developed into very big circuits due to their significant role in Memory design. The sense amplifier plays a significant role in terms of its recital, Functionality and reliability of the memory circuits. Fast access time and low power Dissipation are achieved with newly developed circuits of sense amplifiers for low voltage supply. Static RAM is the sense amplifiers at the ends of the two Complementary bit lines that amplify the small voltages to a normal logic level. Static RAM (SRAM) is a type of random access memory that retains data bits in its Memory as long as power is supplied. The proposed circuit is a P-type metal oxide Semiconductor (PMOS) biased sense amplifier, which provides very high, output Impedance, has reduced sense delay, and has reduced power dissipation. It performs the same operations as conventional circuits. The proposed circuit has a smaller number of transistors, so sensing delay and power consumption are also reduced. These circuits are simulated and examined using the Tanner EDA tool employing 180 nm technology library parameters. Key Words: Low power consumption, Power Consumption, Sense amplifiers, sense delay, static RAM.

DRAM industry has gained most of the interest in the memory chip industry in the last decades for its high density (due to its simple structure) and lower power consumption. As the density of DRAM chips increased, the bit-line parasitic capacitances increased and many problems appeared such as increased power consumption and larger read/write access times which gave great attention to improve the design of the CMOS sense amplifier used in the memory chip for its great effects on memory access time, overall memory power dissipation and chip density. In this paper, we introduce one of the most effective solutions to increase the performance of the advanced high density DRAMs by replacing the sense amplifier circuit with a specially designed logic buffer circuit based on Resonant Tunneling Diode (RTD) that can be fabricated in Nano-scale and exhibit higher operation speed with lower power consumption and higher chip density. The proposed design improves the Power Delay Product (PDP) by about 36% compared with that in conventional RTD-CMOS sense amplifier and 15% compared with that in conventional CMOS sense amplifier. The 45nm CMOS technology is used in this paper.

Researchers have investigated several different sense amplifiers’ yield and other quantitative features. Amplification is required for various power-saving methods, including the sleep transistor, the sleep stack, the sleepy keeper, and others. This study aims to evaluate how much energy is consumed by the many different sense amplifier topologies. Simulations have shown that adopting a sleep transistor approach can significantly reduce the amount of power lost even while operating at 1.2V.

A novel sense-amplifier (SA) based flip-flop (FF) design is proposed to improve power and area efficiency for low-power applications. To reduce transistor count, a logic replacement technique is initially applied to the RS latch design. Following this, the discharge paths of both the sense-amplifier design and RS latch design are merged, effectively removing redundant transistors. This integration reduces layout area and addresses the additional power consumption from glitches observed in previous SAFF designs. These enhancements significantly decrease the clock-to-Q delay and average power consumption, with performance gains confirmed through post-layout simulations and chip measurements.

Recent days sensing technology in the memory play a vital role, in the “Von Neumann Bottleneck” method, there should be a specified memory was given for the read and write operations. The Sense Amplifier is a key circuit in the edge of power efficient, high-speed random-access memories. This paper describes the design of sense amplifier for a given random access memory and more elaborately on Resistive RAM. Reading of the memory is most important in all memories and it is time-consuming, this paper aims to improve the speed of reading in the memories especially in Resistive RAM. Resistive RAM was built on 1Resistor-1Transistor configurations, the data is stored in the form of resistance, and which is non-volatile in nature. From the resistor we can retrieve the data which is in the form of resistance using the time-based sense amplifier. The sense amplified designed to optimize the delay and to improve the speed of sensing. The schematic of sense amplifier is verified using PYXIS environment with 130 nm CMOS-technology node and it works fine and helps us to improve the reading operations efficiently in the Resistive RAM. These are used in many applications and different fields like security, neuromorphic computing, and non-volatile logic system.KeywordsRRAMTime-based sense amplifierNon-volatile1Resistor-1Transistor

Most modern microprocessors have one or two levels of on-chip caches to make things run faster, but this is not always the case. Most of the time, these caches are made of static random access memory cells. They take up a lot of space on the chip and use a lot of electricity. A lot of the time, low power is more important than several aspects. This is true for phones and tablets. Cache memory design for single bit architecture consists of six transistors static random access memory cell, a circuit of write driver, and sense amplifiers (such as voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch sense amplifier, and current latch sense amplifier, all of which are compared on different resistance values in terms of a number of transistors, delay in sensing and consumption of power. The conclusion arises that single bit six transistor static random access memory cell voltage differential sense amplifier architecture consumes 11.34 μW of power which shows that power is reduced up to 83%, 77.75% reduction in the case of the current differential sense amplifier, 39.62% in case of charge transfer differential sense amplifier and 50% in case of voltage latch sense amplifier when compared to existing latch sense amplifier architecture. Furthermore, power reduction techniques are applied over different blocks of cache memory architecture to optimize energy. The single-bit six transistors static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique consumes 8.078 μW of power, i.e., reduce 28% more power that makes single bit six transistor static random access memory cell with forced tack technique and voltage differential sense amplifier with dual sleep technique more energy efficient.

74This chapter describes the Cache Memory Design for Single Bit Architecture for IoT approaches to industrial informatics. Single Bit Architecture composed of six transistors static random access memory cell, a circuit of write driver, voltage differential sense amplifier, current differential sense amplifier, charge transfer differential sense amplifier, voltage latch type sense amplifier, and current latch-type sense amplifiers have been implemented and compared on different values of resistance. Results showed that the cache memory design for singe-bit architecture with voltage differential sense amplifier consumes 11.34 µW of power. Apart from it, power reduction techniques such as power reduction sleep transistor technique, power reduction forced stack technique, power reduction sleepy stack technique, and power reduction dual sleep technique is applied over different blocks of cache memory design for single bit architecture. The conclusion arises that Cache Memory Design for six transistors static random access memory cell with power reduction forced stack technique voltage differential sense amplifier with power reduction dual sleep technique in architecture consume 8.078 µW of power with the lowest 30.48 × 62.613 mm2 of area.

This paper describes a newly developed logic circuit family based on dual-rail bit lines and sense amplifiers that is used extensively in a 1.0-GHz, single-issue, 64-bit PowerPC integer processor, gigahertz unit test site (guTS). The family consists of an incrementor, a count-leading-zero, a rotator, and a read-only memory. Each macro consists of a leaf-cell array, dual-rail bit lines, a row of sense amplifiers, a control block, and peripheral circuits. A common read-out scheme sensing the differential voltage of dual-rail bit lines is used. The hardware was fabricated in a 0.25-/spl mu/m drawn channel length, six-metal-layer (Al) CMOS technology (1.8-V nominal VDD). Wafer testing was performed using a probe card. The macros were tested cycle by cycle by scanning the input data to the read/write address latches and data latches, and scanning the result out from the output receiving latches. Functional testing was performed on guTS macros at frequencies up to 1.0 GHz at 25/spl deg/C with nominal VDD (1.1 GHz for the ROM).